misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

1 files changed, 7 insertions, 6 deletions

diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index ca82d0b45..0c5eeb1bd 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -159,16 +159,17 @@ class TLB : public BaseTLB
 
     // static helper functions... really
     static bool validVirtualAddress(Addr vaddr);
-    static Fault checkCacheability(RequestPtr &req);
-    Fault translateInst(RequestPtr req, ThreadContext *tc);
-    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+    static Fault checkCacheability(const RequestPtr &req);
+    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
+    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
     Fault translateAtomic(
-            RequestPtr req, ThreadContext *tc, Mode mode) override;
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
     void translateTiming(
-            RequestPtr req, ThreadContext *tc,
+            const RequestPtr &req, ThreadContext *tc,
             Translation *translation, Mode mode) override;
     Fault finalizePhysical(
-            RequestPtr req, ThreadContext *tc, Mode mode) const override;
+            const RequestPtr &req,
+            ThreadContext *tc, Mode mode) const override;
 
     // Checkpointing
     void serialize(CheckpointOut &cp) const override;