arch: Create a method to finalize physical addresses

 in the TLB

Some architectures (currently only x86) require some fixing-up of
physical addresses after a normal address translation. This is usually
to remap devices such as the APIC, but could be used for other memory
mapped devices as well. When running the CPU in a using hardware
virtualization, we still need to do these address fix-ups before
inserting the request into the memory system. This patch moves this
patch allows that code to be used by such CPUs without doing full
address translations.

2 files changed, 7 insertions, 0 deletions

diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index de828a625..9c1745cc8 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -333,6 +333,12 @@ TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
     return NoFault;
 }
 
+Fault
+TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
+{
+    return NoFault;
+}
+
 PowerISA::PTE &
 TLB::index(bool advance)
 {
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index 3cf2a3706..753231a89 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -164,6 +164,7 @@ class TLB : public BaseTLB
      *  supported by Checker at the moment
      */
     Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+    Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
 
     // Checkpointing
     void serialize(std::ostream &os);