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| author | Alexandru <alexandru.dutu@amd.com> | 2014-08-28 10:11:44 -0500 |
|---|---|---|
| committer | Alexandru <alexandru.dutu@amd.com> | 2014-08-28 10:11:44 -0500 |
| commit | 5efbb4442a0e8c653539e263bf87c48849280e23 (patch) | |
| tree | da6807c806ebb1f658692c5bf823156831134c9f /src/arch/power | |
| parent | 26ac28dec288e4fd96d999267ec7cafad4d58c5a (diff) | |
| download | gem5-5efbb4442a0e8c653539e263bf87c48849280e23.tar.xz | |
mem: adding architectural page table support for SE mode
This patch enables the use of page tables that are stored in system memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.
Diffstat (limited to 'src/arch/power')
| -rw-r--r-- | src/arch/power/process.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/power/process.hh b/src/arch/power/process.hh index 977b75ae8..b96c77c70 100644 --- a/src/arch/power/process.hh +++ b/src/arch/power/process.hh @@ -58,5 +58,8 @@ class PowerLiveProcess : public LiveProcess void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value); }; +/* No architectural page table defined for this ISA */ +typedef NoArchPageTable ArchPageTable; + #endif // __POWER_PROCESS_HH__ |