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authorGabe Black <gblack@eecs.umich.edu>2012-01-29 02:04:34 -0800
committerGabe Black <gblack@eecs.umich.edu>2012-01-29 02:04:34 -0800
commitdc0e629ea1f074691d307cde3ab7dd51a5e2102f (patch)
tree9ce01152dc0c5231748a2da03199096a87ec34f5 /src/arch/power
parent22a076a6d5b949db5595bbca530fe7db927f6367 (diff)
downloadgem5-dc0e629ea1f074691d307cde3ab7dd51a5e2102f.tar.xz
Implement Ali's review feedback.
Try to decrease indentation, and remove some redundant FullSystem checks.
Diffstat (limited to 'src/arch/power')
-rw-r--r--src/arch/power/tlb.cc13
-rwxr-xr-xsrc/arch/power/vtophys.cc11
2 files changed, 10 insertions, 14 deletions
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 2148e875a..9f535e9e5 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -309,14 +309,13 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
Fault
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
- if (FullSystem) {
+ if (FullSystem)
fatal("translate atomic not yet implemented in full system mode.\n");
- } else {
- if (mode == Execute)
- return translateInst(req, tc);
- else
- return translateData(req, tc, mode == Write);
- }
+
+ if (mode == Execute)
+ return translateInst(req, tc);
+ else
+ return translateData(req, tc, mode == Write);
}
void
diff --git a/src/arch/power/vtophys.cc b/src/arch/power/vtophys.cc
index 597f41b2f..b03f507fc 100755
--- a/src/arch/power/vtophys.cc
+++ b/src/arch/power/vtophys.cc
@@ -1,6 +1,5 @@
/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2012 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,9 +25,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Ali Saidi
- * Nathan Binkert
- * Jaidev Patwardhan
+ * Authors: Gabe Black
*/
#include "arch/power/vtophys.hh"
@@ -38,12 +35,12 @@ using namespace std;
Addr
PowerISA::vtophys(Addr vaddr)
{
- fatal("VTOPHYS: Unimplemented on POWER\n");
+ fatal("vtophys: Unimplemented on POWER\n");
}
Addr
PowerISA::vtophys(ThreadContext *tc, Addr addr)
{
- fatal("VTOPHYS: Unimplemented on POWER\n");
+ fatal("vtophys: Unimplemented on POWER\n");
}