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authorAlexandru Dutu <alexandru.dutu@amd.com>2014-11-23 18:01:09 -0800
committerAlexandru Dutu <alexandru.dutu@amd.com>2014-11-23 18:01:09 -0800
commit1f539f13c32ad5a9187d56a098d4c857639b0e05 (patch)
tree7618c3b946d9c25d9b22018f226eee77b6de4aaf /src/arch/power
parentc11bcb8119273ef91c40a25b8fd9471a887d0ee5 (diff)
downloadgem5-1f539f13c32ad5a9187d56a098d4c857639b0e05.tar.xz
mem: Page Table map api modification
This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes.
Diffstat (limited to 'src/arch/power')
-rw-r--r--src/arch/power/tlb.hh6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index 9ea1fca8b..0abafc777 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -62,9 +62,13 @@ struct TlbEntry
{
}
- TlbEntry(Addr asn, Addr vaddr, Addr paddr)
+ TlbEntry(Addr asn, Addr vaddr, Addr paddr,
+ bool uncacheable, bool read_only)
: _pageStart(paddr)
{
+ if (uncacheable || read_only)
+ warn("Power TlbEntry does not support uncacheable"
+ " or read-only mappings\n");
}
void