revert 5af8f40d8f2c

4 files changed, 1 insertions, 21 deletions

diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc
index 5bd16b40d..087e1f740 100644
--- a/src/arch/power/insts/static_inst.cc
+++ b/src/arch/power/insts/static_inst.cc
@@ -57,8 +57,6 @@ PowerStaticInst::printReg(std::ostream &os, int reg) const
         }
       case CCRegClass:
         panic("printReg: POWER does not implement CCRegClass\n");
-      case VectorRegClass:
-        panic("printReg: POWER does not implement VectorRegClass\n");
     }
 }
 
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 08ee82d5d..aaf5bd92a 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -105,13 +105,6 @@ class ISA : public SimObject
         return reg;
     }
 
-    // dummy
-    int
-    flattenVectorIndex(int reg) const
-    {
-        return reg;
-    }
-
     int
     flattenMiscIndex(int reg) const
     {
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 1d0b4a21f..abee516fc 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -55,12 +55,6 @@ typedef uint64_t MiscReg;
 // dummy typedef since we don't have CC regs
 typedef uint8_t CCReg;
 
-// typedefs for Vector registers
-const int NumVectorRegElements = 0;
-typedef uint64_t VectorRegElement;
-const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
-typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
-
 // Constants Related to the number of registers
 const int NumIntArchRegs = 32;
 
@@ -74,7 +68,6 @@ const int NumInternalProcRegs = 0;
 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
 const int NumCCRegs = 0;
-const int NumVectorRegs = 0;
 const int NumMiscRegs = NUM_MISCREGS;
 
 // Semantically meaningful register indices
@@ -97,8 +90,7 @@ const int SyscallSuccessReg = 3;
 // These help enumerate all the registers for dependence tracking.
 const int FP_Reg_Base = NumIntRegs;
 const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
-const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
-const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs; // NumVectorRegs == 0
+const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
 
 typedef union {
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index fa2a1d89b..7be195b8d 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -51,9 +51,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     // Would need to add condition-code regs if implemented
     assert(NumCCRegs == 0);
 
-    // Copy vector registers when vector registers put to use.
-    assert(NumVectorRegs == 0);
-
     // Copy misc. registers
     copyMiscRegs(src, dest);