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| author | Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> | 2017-04-05 13:14:34 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | a473b5a6eb269cc303ecfb5e5643d891a5d255d9 (patch) | |
| tree | 4fde47e5c62c566f81d13f6e90ad98cca781ff6e /src/arch/power | |
| parent | 43d833246fcfe092a0c08dde1fdf7e3d409d1af9 (diff) | |
| download | gem5-a473b5a6eb269cc303ecfb5e5643d891a5d255d9.tar.xz | |
cpu: Simplify the rename interface and use RegId
With the hierarchical RegId there are a lot of functions that are
redundant now.
The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.
Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702
Diffstat (limited to 'src/arch/power')
| -rw-r--r-- | src/arch/power/insts/branch.cc | 2 | ||||
| -rw-r--r-- | src/arch/power/insts/static_inst.cc | 18 | ||||
| -rw-r--r-- | src/arch/power/isa.hh | 3 |
3 files changed, 11 insertions, 12 deletions
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc index f10e8453a..d13a0a7d3 100644 --- a/src/arch/power/insts/branch.cc +++ b/src/arch/power/insts/branch.cc @@ -153,7 +153,7 @@ BranchNonPCRelCond::generateDisassembly(Addr pc, PowerISA::PCState BranchRegCond::branchTarget(ThreadContext *tc) const { - uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].regIdx); + uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].index()); return regVal & 0xfffffffc; } diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc index 210205db2..85f9cf628 100644 --- a/src/arch/power/insts/static_inst.cc +++ b/src/arch/power/insts/static_inst.cc @@ -38,15 +38,12 @@ using namespace PowerISA; void PowerStaticInst::printReg(std::ostream &os, RegId reg) const { - switch (reg.regClass) { - case IntRegClass: - ccprintf(os, "r%d", reg.regIdx); - break; - case FloatRegClass: - ccprintf(os, "f%d", reg.regIdx); - break; - case MiscRegClass: - switch (reg.regIdx) { + if (reg.isIntReg()) + ccprintf(os, "r%d", reg.index()); + else if (reg.isFloatReg()) + ccprintf(os, "f%d", reg.index()); + else if (reg.isMiscReg()) + switch (reg.index()) { case 0: ccprintf(os, "cr"); break; case 1: ccprintf(os, "xer"); break; case 2: ccprintf(os, "lr"); break; @@ -54,9 +51,8 @@ PowerStaticInst::printReg(std::ostream &os, RegId reg) const default: ccprintf(os, "unknown_reg"); break; } - case CCRegClass: + else if (reg.isCCReg()) panic("printReg: POWER does not implement CCRegClass\n"); - } } std::string diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index aaf5bd92a..475b4d2f8 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -36,6 +36,7 @@ #include "arch/power/registers.hh" #include "arch/power/types.hh" #include "base/misc.hh" +#include "cpu/reg_class.hh" #include "sim/sim_object.hh" struct PowerISAParams; @@ -86,6 +87,8 @@ class ISA : public SimObject fatal("Power does not currently have any misc regs defined\n"); } + RegId flattenRegId(const RegId& regId) const { return regId; } + int flattenIntIndex(int reg) const { |