diff options
| author | Gabe Black <gabeblack@google.com> | 2018-11-19 18:14:16 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:02:05 +0000 |
| commit | 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 (patch) | |
| tree | 22cc08624db8bfa11e4ea7c9817a864ebc2ea706 /src/arch/power | |
| parent | 25474167e5b247d1b91fbf802c5b396a63ae705e (diff) | |
| download | gem5-5edfb67041ad1c246f4ceca147f06b9db3c0ecc3.tar.xz | |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/power')
| -rw-r--r-- | src/arch/power/registers.hh | 2 | ||||
| -rw-r--r-- | src/arch/power/remote_gdb.cc | 4 | ||||
| -rw-r--r-- | src/arch/power/utility.cc | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh index e8de218e7..909c24e96 100644 --- a/src/arch/power/registers.hh +++ b/src/arch/power/registers.hh @@ -49,7 +49,7 @@ const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1; typedef RegVal IntReg; // Floating point register file entry type -typedef RegVal FloatRegBits; +typedef RegVal FloatReg; typedef RegVal MiscReg; // dummy typedef since we don't have CC regs diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc index b4082e0ee..c8a71c5e7 100644 --- a/src/arch/power/remote_gdb.cc +++ b/src/arch/power/remote_gdb.cc @@ -184,7 +184,7 @@ RemoteGDB::PowerGdbRegCache::getRegs(ThreadContext *context) r.gpr[i] = htobe((uint32_t)context->readIntReg(i)); for (int i = 0; i < NumFloatArchRegs; i++) - r.fpr[i] = context->readFloatRegBits(i); + r.fpr[i] = context->readFloatReg(i); r.pc = htobe((uint32_t)context->pcState().pc()); r.msr = 0; // Is MSR modeled? @@ -203,7 +203,7 @@ RemoteGDB::PowerGdbRegCache::setRegs(ThreadContext *context) const context->setIntReg(i, betoh(r.gpr[i])); for (int i = 0; i < NumFloatArchRegs; i++) - context->setFloatRegBits(i, r.fpr[i]); + context->setFloatReg(i, r.fpr[i]); context->pcState(betoh(r.pc)); // Is MSR modeled? diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc index c8ff99988..6738c1289 100644 --- a/src/arch/power/utility.cc +++ b/src/arch/power/utility.cc @@ -47,7 +47,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest) // Then loop through the floating point registers. for (int i = 0; i < NumFloatRegs; ++i) - dest->setFloatRegBits(i, src->readFloatRegBits(i)); + dest->setFloatReg(i, src->readFloatReg(i)); // Would need to add condition-code regs if implemented assert(NumCCRegs == 0); |