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| author | Chuan Zhu <chuan.zhu@arm.com> | 2018-01-23 10:19:07 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-16 09:29:38 +0000 |
| commit | 94553f32d8dbb7979dbeb0e6bafaa5db1985db1e (patch) | |
| tree | 643680b58619faa61bbf173aa549f12cc1e5f730 /src/arch/riscv/RiscvISA.py | |
| parent | c105793a2027cd113233e8ce6c5e2d4ea2f9cded (diff) | |
| download | gem5-94553f32d8dbb7979dbeb0e6bafaa5db1985db1e.tar.xz | |
arch-arm: Fix syntax error in TLB::getResultTe
The patch fixes one syntax error in TLB::getResultTe
Change-Id: I31a72a52d5c03f43929a69ca1be61d9c20e76f5b
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7983
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/riscv/RiscvISA.py')
0 files changed, 0 insertions, 0 deletions