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| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-24 18:38:06 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-29 15:53:02 +0000 |
| commit | 8ad26e2688b8736f9290086bb4026cc7500429e9 (patch) | |
| tree | 5f3a00fbdc27d106006f62077817ba290a9c88ff /src/arch/riscv/RiscvInterrupts.py | |
| parent | 2209b35832d63e0367ef5f26e388a162899af21d (diff) | |
| download | gem5-8ad26e2688b8736f9290086bb4026cc7500429e9.tar.xz | |
cpu: Don't override ISA if provided by user
The BaseCPU.createThreads() method currently overrides the BaseCPU.isa
parameter. This is sometimes undesirable. Change the behavior so that
the default value for the isa parameter is the empty list and teach
createThreads() to only override the ISA if none has been specified.
Change-Id: I2ac5535e55fc57057e294d3c6a93088b33bf7b84
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6121
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/RiscvInterrupts.py')
0 files changed, 0 insertions, 0 deletions