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author | Jose Marinho <jose.marinho@arm.com> | 2017-07-20 14:57:39 +0100 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-21 17:09:18 +0000 |
commit | 760cc5735f48f3a5a52ebe31df0c039b23c3d611 (patch) | |
tree | da4103b240221359838888467ac4f12544acc2c5 /src/arch/riscv/RiscvInterrupts.py | |
parent | 00232a868e4816d19c129fb3d6ef5519d7176d5a (diff) | |
download | gem5-760cc5735f48f3a5a52ebe31df0c039b23c3d611.tar.xz |
cpu, cpu, sim: move Cycle probe update
Move the code responsible for performing the actual probe point notify
into BaseCPU. Use BaseCPU activateContext and suspendContext to keep
track of sleep cycles. Create a probe point (ppActiveCycles) that does
not count cycles where the processor was asleep. Rename ppCycles
to ppAllCycles to reflect its nature.
Change-Id: I1907ddd07d0ff9f2ef22cc9f61f5f46c630c9d66
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5762
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/RiscvInterrupts.py')
0 files changed, 0 insertions, 0 deletions