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| author | Gabe Black <gabeblack@google.com> | 2019-09-02 21:26:12 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-10-19 01:45:48 +0000 |
| commit | ae390c629f2a10fd6a1c2eb50b7d3510d6e091da (patch) | |
| tree | 51f12635838755ef7519bea1c72bfb96e0214336 /src/arch/riscv/RiscvInterrupts.py | |
| parent | 1c047f8b92f5708bbef50d24cf47902d5da313e3 (diff) | |
| download | gem5-ae390c629f2a10fd6a1c2eb50b7d3510d6e091da.tar.xz | |
arch: Make a base class for Interrupts.
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.
Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/riscv/RiscvInterrupts.py')
| -rw-r--r-- | src/arch/riscv/RiscvInterrupts.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/RiscvInterrupts.py b/src/arch/riscv/RiscvInterrupts.py index 57b29b4ca..7e63dedea 100644 --- a/src/arch/riscv/RiscvInterrupts.py +++ b/src/arch/riscv/RiscvInterrupts.py @@ -31,9 +31,9 @@ # Sven Karlsson # Alec Roelke -from m5.SimObject import SimObject +from m5.objects.BaseInterrupts import BaseInterrupts -class RiscvInterrupts(SimObject): +class RiscvInterrupts(BaseInterrupts): type = 'RiscvInterrupts' cxx_class = 'RiscvISA::Interrupts' cxx_header = 'arch/riscv/interrupts.hh' |