arch-riscv: enable rudimentary fs simulation

These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.

Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 13 insertions, 0 deletions

diff --git a/src/arch/riscv/RiscvSystem.py b/src/arch/riscv/RiscvSystem.py
index c64e363fc..071b211a2 100644
--- a/src/arch/riscv/RiscvSystem.py
+++ b/src/arch/riscv/RiscvSystem.py
@@ -28,10 +28,23 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Alec Roelke
+#          Robert Scheffel
 
+from m5.params import *
 from System import System
 
+
 class RiscvSystem(System):
     type = 'RiscvSystem'
     cxx_header = 'arch/riscv/system.hh'
+    bare_metal = Param.Bool(False, "Using Bare Metal Application?")
+    reset_vect = Param.Addr(0x0, 'Reset vector')
     load_addr_mask = 0xFFFFFFFFFFFFFFFF
+
+
+class BareMetalRiscvSystem(RiscvSystem):
+    type = 'BareMetalRiscvSystem'
+    cxx_header = 'arch/riscv/bare_metal/system.hh'
+    bootloader = Param.String("File, that contains the bootloader code")
+
+    bare_metal = True