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| author | Boris Shingarov <shingarov@gmail.com> | 2017-09-18 15:30:51 -0400 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-10-17 08:35:23 +0000 |
| commit | 1b63b756cc6ca75acceee51397f815df06fb0dff (patch) | |
| tree | ae547d9e5f23dab6f86a5efa85e4da70ad0f3131 /src/arch/riscv/RiscvTLB.py | |
| parent | 5a7ac72aa106a34f12662b3cd2da8dab47b668a0 (diff) | |
| download | gem5-1b63b756cc6ca75acceee51397f815df06fb0dff.tar.xz | |
arch-arm: Fix inverted 32/64-bit check in GDB
Change-Id: Ided438af19c9b8504d4624119c4d9fb5157c7cf0
Reviewed-on: https://gem5-review.googlesource.com/4720
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/riscv/RiscvTLB.py')
0 files changed, 0 insertions, 0 deletions