diff options
| author | Gabe Black <gabeblack@google.com> | 2018-09-11 00:57:34 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-09-11 21:39:13 +0000 |
| commit | 6c49198b7541eeddf648e210569e18eb0ab79303 (patch) | |
| tree | ce38f2a455d76780723747f94a2bddf87acdc3b1 /src/arch/riscv/RiscvTLB.py | |
| parent | 1023a92971a32cdfa58e119b5fe62b91d580e729 (diff) | |
| download | gem5-6c49198b7541eeddf648e210569e18eb0ab79303.tar.xz | |
base: Correct a small typo in sim/core.(hh|cc).
The value GHz with a small z was spelled GHZ with a large z, which was
inconsistent with the other frequency-like values in that namespace.
Change-Id: I55dfc447a5811ae584e46769cd9cadd08bd1e716
Reviewed-on: https://gem5-review.googlesource.com/12572
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/riscv/RiscvTLB.py')
0 files changed, 0 insertions, 0 deletions