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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-24 09:55:19 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 15:47:55 +0000 |
| commit | 06f1259a4054643eb02b183560478021442be91e (patch) | |
| tree | 236d5417dd33e63a7ec78343f21b11047aa8092c /src/arch/riscv/SConsopts | |
| parent | b9bf7935f38e13f05c6d85916ae1578ebc5d5acb (diff) | |
| download | gem5-06f1259a4054643eb02b183560478021442be91e.tar.xz | |
arch-arm: Init AArch64 ID registers in SE mode
One of the auxv vector's flag is the HWCAP, whose bits match the content
of several arm ID registers. This patch factors out AArch64 ID
registers init into a separate method and creates the symmetric AArch32
ID register init as well, so that we get a meaningful auxiliary vector
in SE mode.
Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13064
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/riscv/SConsopts')
0 files changed, 0 insertions, 0 deletions