arch-riscv: enable rudimentary fs simulation

These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.

Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 68 insertions, 0 deletions

diff --git a/src/arch/riscv/bare_metal/system.cc b/src/arch/riscv/bare_metal/system.cc
new file mode 100644
index 000000000..5cbd63af2
--- /dev/null
+++ b/src/arch/riscv/bare_metal/system.cc
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018 TU Dresden
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Robert Scheffel
+ */
+
+#include "arch/riscv/bare_metal/system.hh"
+
+#include "base/loader/object_file.hh"
+
+BareMetalRiscvSystem::BareMetalRiscvSystem(Params *p)
+    : RiscvSystem(p),
+      bootloader(createObjectFile(p->bootloader))
+{
+    if (bootloader == NULL) {
+         fatal("Could not load bootloader file %s", p->bootloader);
+    }
+
+    _resetVect = bootloader->entryPoint();
+}
+
+BareMetalRiscvSystem::~BareMetalRiscvSystem()
+{
+    delete bootloader;
+}
+
+void
+BareMetalRiscvSystem::initState()
+{
+    // Call the initialisation of the super class
+    RiscvSystem::initState();
+
+    // load program sections into memory
+    if (!bootloader->loadSections(physProxy)) {
+        warn("could not load sections to memory");
+    }
+}
+
+BareMetalRiscvSystem *
+BareMetalRiscvSystemParams::create()
+{
+    return new BareMetalRiscvSystem(this);
+}
+