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author | Alec Roelke <ar4jc@virginia.edu> | 2017-07-13 14:24:06 -0400 |
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committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-14 20:29:25 +0000 |
commit | 68b6f9c8a1819fdeee737cf369cc6a499b505a6c (patch) | |
tree | 5e83244b5105e118d9634e88816b8e8531e4f739 /src/arch/riscv/decoder.cc | |
parent | d72eafa64b4313f30f4c7a25000ff04f5cf30380 (diff) | |
download | gem5-68b6f9c8a1819fdeee737cf369cc6a499b505a6c.tar.xz |
riscv: Fix bugs with RISC-V decoder and detailed CPUs
This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen. The rest of these
assertions will be changed in a later patch.
[Remove commented-out debugging line and add clarifying comment to
registerName in utility.hh.]
Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
Reviewed-on: https://gem5-review.googlesource.com/4041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/decoder.cc')
-rw-r--r-- | src/arch/riscv/decoder.cc | 48 |
1 files changed, 31 insertions, 17 deletions
diff --git a/src/arch/riscv/decoder.cc b/src/arch/riscv/decoder.cc index 36504f4f8..020c5e34e 100644 --- a/src/arch/riscv/decoder.cc +++ b/src/arch/riscv/decoder.cc @@ -37,29 +37,45 @@ namespace RiscvISA { +static const MachInst LowerBitMask = (1 << sizeof(MachInst) * 4) - 1; +static const MachInst UpperBitMask = LowerBitMask << sizeof(MachInst) * 4; + +void Decoder::reset() +{ + aligned = true; + mid = false; + more = true; + emi = NoopMachInst; + instDone = false; +} + void Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) { - DPRINTF(Decode, "Getting bytes 0x%08x from address %#x\n", - inst, pc.pc()); + DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst, + fetchPC); bool aligned = pc.pc() % sizeof(MachInst) == 0; - if (mid) { - assert(!aligned); - emi |= (inst & 0xFFFF) << 16; + if (aligned) { + emi = inst; + if (compressed(emi)) + emi &= LowerBitMask; + more = !compressed(emi); instDone = true; } else { - MachInst instChunk = aligned ? inst & 0xFFFF : - (inst & 0xFFFF0000) >> 16; - if (aligned) { - emi = (inst & 0x3) < 0x3 ? instChunk : inst; + if (mid) { + assert((emi & UpperBitMask) == 0); + emi |= (inst & LowerBitMask) << sizeof(MachInst)*4; + mid = false; + more = false; instDone = true; } else { - emi = instChunk; - instDone = (instChunk & 0x3) < 0x3; + emi = (inst & UpperBitMask) >> sizeof(MachInst)*4; + mid = !compressed(emi); + more = true; + instDone = compressed(emi); } } - mid = !instDone; } StaticInstPtr @@ -83,12 +99,10 @@ Decoder::decode(RiscvISA::PCState &nextPC) return nullptr; instDone = false; - if ((emi & 0x3) < 0x3) { - nextPC.compressed(true); - nextPC.npc(nextPC.pc() + sizeof(MachInst)/2); + if (compressed(emi)) { + nextPC.npc(nextPC.instAddr() + sizeof(MachInst) / 2); } else { - nextPC.compressed(false); - nextPC.npc(nextPC.pc() + sizeof(MachInst)); + nextPC.npc(nextPC.instAddr() + sizeof(MachInst)); } return decode(emi, nextPC.instAddr()); |