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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-15 09:57:00 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-20 13:30:02 +0000 |
| commit | a7083ece990adddfd3bec8b48c5db7dee1781d55 (patch) | |
| tree | b969138bafaf25660481fb79328775f1f3641c63 /src/arch/riscv/decoder.cc | |
| parent | 657d4054ea36e6af8959f2fa7bcfd79b7c887cfd (diff) | |
| download | gem5-a7083ece990adddfd3bec8b48c5db7dee1781d55.tar.xz | |
arch-arm: Adding isa templates for semihosting ops
A new class of Semihosting constructor templates has been added. Their
main purpose is to check if the Exception Generation Instructions (HLT,
SVC) are actually a semihosting command. If that is the case, the
IsMemBarrier flag is raised, so that in the O3 model we perform a
coherent memory access during the semihosting operation.
Change-Id: Ib87fdeb70ee7a930659563230a80cce0e1372c32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8370
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/riscv/decoder.cc')
0 files changed, 0 insertions, 0 deletions