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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-05-16 17:00:02 -0400 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-05-23 19:10:18 +0000 |
| commit | 76692f360c243401a850ea74cf123d4d006113ec (patch) | |
| tree | 8b1b6fcf7919ad7b0eb11b2e2eb88edd3b3889c0 /src/arch/riscv/decoder.hh | |
| parent | 1d10cd6185edfd46d51f6562bff832a9b5d36cff (diff) | |
| download | gem5-76692f360c243401a850ea74cf123d4d006113ec.tar.xz | |
arch-riscv: Fix bad stack initialization
This patch fixes a problem with RISC-V initial stack setup in SE mode
where the AT_RANDOM aux vector value contains an address that is too
close to the top of the stack and doesn't fit the required 16 bytes. To
fix this, the program header table was added to the top of the stack
just like the RISC-V proxy kernel does.
Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3
Reviewed-on: https://gem5-review.googlesource.com/3401
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/decoder.hh')
0 files changed, 0 insertions, 0 deletions