arch-riscv: Add support for compressed extension RV64C

This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C.  Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).

[Update diassembly generation for new RegId type.]
[Rebase onto master.]

Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Reviewed-on: https://gem5-review.googlesource.com/3860
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

1 files changed, 17 insertions, 47 deletions

diff --git a/src/arch/riscv/decoder.hh b/src/arch/riscv/decoder.hh
index b1d91d610..ef644fa13 100644
--- a/src/arch/riscv/decoder.hh
+++ b/src/arch/riscv/decoder.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2012 Google
+ * Copyright (c) 2017 The University of Virginia
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,16 +27,19 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Gabe Black
+ *          Alec Roelke
  */
 
 #ifndef __ARCH_RISCV_DECODER_HH__
 #define __ARCH_RISCV_DECODER_HH__
 
 #include "arch/generic/decode_cache.hh"
+#include "arch/riscv/isa_traits.hh"
 #include "arch/riscv/types.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
+#include "debug/Decode.hh"
 
 namespace RiscvISA
 {
@@ -43,73 +47,39 @@ namespace RiscvISA
 class ISA;
 class Decoder
 {
+  private:
+    DecodeCache::InstMap instMap;
+    bool mid;
+
   protected:
     //The extended machine instruction being generated
     ExtMachInst emi;
     bool instDone;
 
   public:
-    Decoder(ISA* isa = nullptr) : instDone(false)
+    Decoder(ISA* isa=nullptr)
+        : mid(false), emi(NoopMachInst), instDone(false)
     {}
 
-    void
-    process()
-    {
-    }
-
-    void
-    reset()
-    {
-        instDone = false;
-    }
+    void process() {}
+    void reset() { instDone = false; }
 
     //Use this to give data to the decoder. This should be used
     //when there is control flow.
-    void
-    moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
-    {
-        emi = inst;
-        instDone = true;
-    }
-
-    bool
-    needMoreBytes()
-    {
-        return true;
-    }
-
-    bool
-    instReady()
-    {
-        return instDone;
-    }
+    void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
 
+    bool needMoreBytes() { return true; }
+    bool instReady() { return instDone; }
     void takeOverFrom(Decoder *old) {}
 
-  protected:
-    /// A cache of decoded instruction objects.
-    static GenericISA::BasicDecodeCache defaultCache;
-
-  public:
     StaticInstPtr decodeInst(ExtMachInst mach_inst);
 
     /// Decode a machine instruction.
     /// @param mach_inst The binary instruction to decode.
     /// @retval A pointer to the corresponding StaticInst object.
-    StaticInstPtr
-    decode(ExtMachInst mach_inst, Addr addr)
-    {
-        return defaultCache.decode(this, mach_inst, addr);
-    }
+    StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
 
-    StaticInstPtr
-    decode(RiscvISA::PCState &nextPC)
-    {
-        if (!instDone)
-            return nullptr;
-        instDone = false;
-        return decode(emi, nextPC.instAddr());
-    }
+    StaticInstPtr decode(RiscvISA::PCState &nextPC);
 };
 
 } // namespace RiscvISA