arch-riscv: enable rudimentary fs simulation

These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.

Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 4e44d43f0..ce4cb3846 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2018 TU Dresden
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,10 +28,13 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Alec Roelke
+ *          Robert Scheffel
  */
 #include "arch/riscv/faults.hh"
 
+#include "arch/riscv/system.hh"
 #include "arch/riscv/utility.hh"
+#include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "sim/debug.hh"
 #include "sim/full_system.hh"
@@ -56,6 +60,18 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
     }
 }
 
+void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
+{
+    if (FullSystem) {
+        tc->getCpuPtr()->clearInterrupts(tc->threadId());
+        tc->clearArchRegs();
+    }
+
+    // Advance the PC to the implementation-defined reset vector
+    PCState pc = static_cast<RiscvSystem *>(tc->getSystemPtr())->resetVect();
+    tc->pcState(pc);
+}
+
 void
 UnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst)
 {