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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-07-13 14:24:06 -0400 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-14 20:29:25 +0000 |
| commit | 68b6f9c8a1819fdeee737cf369cc6a499b505a6c (patch) | |
| tree | 5e83244b5105e118d9634e88816b8e8531e4f739 /src/arch/riscv/faults.cc | |
| parent | d72eafa64b4313f30f4c7a25000ff04f5cf30380 (diff) | |
| download | gem5-68b6f9c8a1819fdeee737cf369cc6a499b505a6c.tar.xz | |
riscv: Fix bugs with RISC-V decoder and detailed CPUs
This patch fixes some bugs that were missed with the changes to the
decoder that enabled compatibility with compressed instructions. In
order to accommodate speculation with variable instruction widths, a few
assertions in decoder had to be changed to returning faults as the
specification describes should normally happen. The rest of these
assertions will be changed in a later patch.
[Remove commented-out debugging line and add clarifying comment to
registerName in utility.hh.]
Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95
Reviewed-on: https://gem5-review.googlesource.com/4041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/faults.cc')
| -rw-r--r-- | src/arch/riscv/faults.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc index 58baa4e32..4e44d43f0 100644 --- a/src/arch/riscv/faults.cc +++ b/src/arch/riscv/faults.cc @@ -64,6 +64,13 @@ UnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) } void +IllegalInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) +{ + panic("Illegal instruction 0x%08x at pc 0x%016llx: %s", inst->machInst, + tc->pcState().pc(), reason.c_str()); +} + +void UnimplementedFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) { |