arch-riscv: enable rudimentary fs simulation

These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.

Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 23 insertions, 0 deletions

diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 1e33b648f..478bfd27e 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2016 RISC-V Foundation
  * Copyright (c) 2016 The University of Virginia
+ * Copyright (c) 2018 TU Dresden
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Alec Roelke
+ *          Robert Scheffel
  */
 
 #ifndef __ARCH_RISCV_FAULTS_HH__
@@ -104,6 +106,27 @@ class RiscvFault : public FaultBase
     invoke(ThreadContext *tc, const StaticInstPtr &inst);
 };
 
+class Reset : public FaultBase
+{
+
+    public:
+        Reset()
+            : _name("reset")
+        {}
+
+        FaultName
+        name() const override
+        {
+            return _name;
+        }
+
+        void
+        invoke(ThreadContext *tc, const StaticInstPtr &inst =
+            StaticInst::nullStaticInstPtr) override;
+
+    private:
+        const FaultName _name;
+};
 
 class UnknownInstFault : public RiscvFault
 {