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author | Alec Roelke <ar4jc@virginia.edu> | 2018-02-18 22:28:44 -0500 |
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committer | Alec Roelke <alec.roelke@gmail.com> | 2019-01-16 00:20:34 +0000 |
commit | a3be0a4cbc2665b91e1d83e25cfe709dd100ce5d (patch) | |
tree | dc6cd42d2b244975ad06a40beac9f33722cca3b9 /src/arch/riscv/faults.hh | |
parent | c5baffb5303e9c49d9d475e38783cdcf3391a9a4 (diff) | |
download | gem5-a3be0a4cbc2665b91e1d83e25cfe709dd100ce5d.tar.xz |
arch-riscv: Fix reset function and style
In addition to fixing some style issues with resetting, this patch fixes
what happens on reset. The RISC-V privileged ISA reference manual says
that,
on reset:
1. Privilege mode is set to M
2. mstatus.mie <- 0; mstatus.mprv <- 0
3. PC <- reset vector
4. mcause <- reset cause (0 if there is no distinguishing causes)
5. Everything else is undefined
Because of 5, everything else will be left alone
Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
Reviewed-on: https://gem5-review.googlesource.com/c/14376
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/faults.hh')
-rw-r--r-- | src/arch/riscv/faults.hh | 23 |
1 files changed, 7 insertions, 16 deletions
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh index d9cb44c3d..2176f889b 100644 --- a/src/arch/riscv/faults.hh +++ b/src/arch/riscv/faults.hh @@ -95,24 +95,15 @@ class RiscvFault : public FaultBase class Reset : public FaultBase { + private: + const FaultName _name; - public: - Reset() - : _name("reset") - {} - - FaultName - name() const override - { - return _name; - } - - void - invoke(ThreadContext *tc, const StaticInstPtr &inst = - StaticInst::nullStaticInstPtr) override; + public: + Reset() : _name("reset") {} + FaultName name() const override { return _name; } - private: - const FaultName _name; + void invoke(ThreadContext *tc, const StaticInstPtr &inst = + StaticInst::nullStaticInstPtr) override; }; class InstFault : public RiscvFault |