diff options
| author | Alec Roelke <ar4jc@virginia.edu> | 2017-11-07 15:19:56 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-11-29 00:58:23 +0000 |
| commit | 719ddf73afa62735881ac68acf681abe1bf3bd17 (patch) | |
| tree | 71ba0ac50a066504c9df48cde18ba65f2da05689 /src/arch/riscv/insts/bitfields.hh | |
| parent | 19ad3c4ae46426e988602d870dc2c27fee1154f1 (diff) | |
| download | gem5-719ddf73afa62735881ac68acf681abe1bf3bd17.tar.xz | |
arch-riscv: Move parts of mem insts out of ISA
This patch moves static portions of the memory instructions out of the
ISA generated code and puts them into arch/riscv/insts. It also
simplifies the definitions of load and store instructions by giving
them a common base class.
Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803
Reviewed-on: https://gem5-review.googlesource.com/6024
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/insts/bitfields.hh')
| -rw-r--r-- | src/arch/riscv/insts/bitfields.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/riscv/insts/bitfields.hh b/src/arch/riscv/insts/bitfields.hh index d6648227e..eac070e7f 100644 --- a/src/arch/riscv/insts/bitfields.hh +++ b/src/arch/riscv/insts/bitfields.hh @@ -5,6 +5,9 @@ #define CSRIMM bits(machInst, 19, 15) #define FUNCT12 bits(machInst, 31, 20) +#define IMM5 bits(machInst, 11, 7) +#define IMM7 bits(machInst, 31, 25) +#define IMMSIGN bits(machInst, 31) #define OPCODE bits(machInst, 6, 0) #endif // __ARCH_RISCV_BITFIELDS_HH__
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