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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-11-07 12:11:11 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-11-29 00:57:23 +0000 |
| commit | 19ad3c4ae46426e988602d870dc2c27fee1154f1 (patch) | |
| tree | e9507c51086e8c2f9f5f250f899d5dcb47e20a95 /src/arch/riscv/insts/bitfields.hh | |
| parent | eb02066b31c85d22c67d1ead61048c196653ba1f (diff) | |
| download | gem5-19ad3c4ae46426e988602d870dc2c27fee1154f1.tar.xz | |
arch-riscv: Move unknown out of ISA description
This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts. Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.
Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
Reviewed-on: https://gem5-review.googlesource.com/6023
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/insts/bitfields.hh')
| -rw-r--r-- | src/arch/riscv/insts/bitfields.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/riscv/insts/bitfields.hh b/src/arch/riscv/insts/bitfields.hh index 45744e081..d6648227e 100644 --- a/src/arch/riscv/insts/bitfields.hh +++ b/src/arch/riscv/insts/bitfields.hh @@ -5,5 +5,6 @@ #define CSRIMM bits(machInst, 19, 15) #define FUNCT12 bits(machInst, 31, 20) +#define OPCODE bits(machInst, 6, 0) #endif // __ARCH_RISCV_BITFIELDS_HH__
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