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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-11-07 14:15:41 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-11-29 00:55:46 +0000 |
| commit | eb02066b31c85d22c67d1ead61048c196653ba1f (patch) | |
| tree | 1ab43820091dcf702bf2e7ed083eb27bd3cfb313 /src/arch/riscv/insts/bitfields.hh | |
| parent | d3ecb5d406a3dc12c53a20c271db3027b8477c39 (diff) | |
| download | gem5-eb02066b31c85d22c67d1ead61048c196653ba1f.tar.xz | |
arch-riscv: Move standard ops out of ISA
This patch removes static portions of the standard instruction types
from the generated ISA code and puts them into arch/riscv/insts. Some
dynamically-generated content is left behind for each individual
instruction's implementation. Also, BranchOp is removed due to its
similarity with ImmOp and ImmOp and UImmOp are joined into a single
templated class, ImmOp<T>.
Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
Reviewed-on: https://gem5-review.googlesource.com/6022
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/insts/bitfields.hh')
| -rw-r--r-- | src/arch/riscv/insts/bitfields.hh | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/riscv/insts/bitfields.hh b/src/arch/riscv/insts/bitfields.hh new file mode 100644 index 000000000..45744e081 --- /dev/null +++ b/src/arch/riscv/insts/bitfields.hh @@ -0,0 +1,9 @@ +#ifndef __ARCH_RISCV_BITFIELDS_HH__ +#define __ARCH_RISCV_BITFIELDS_HH__ + +#include "base/bitfield.hh" + +#define CSRIMM bits(machInst, 19, 15) +#define FUNCT12 bits(machInst, 31, 20) + +#endif // __ARCH_RISCV_BITFIELDS_HH__
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