summaryrefslogtreecommitdiff
path: root/src/arch/riscv/insts
diff options
context:
space:
mode:
authorAlec Roelke <ar4jc@virginia.edu>2017-11-07 14:15:41 -0500
committerAlec Roelke <ar4jc@virginia.edu>2017-11-29 00:55:46 +0000
commiteb02066b31c85d22c67d1ead61048c196653ba1f (patch)
tree1ab43820091dcf702bf2e7ed083eb27bd3cfb313 /src/arch/riscv/insts
parentd3ecb5d406a3dc12c53a20c271db3027b8477c39 (diff)
downloadgem5-eb02066b31c85d22c67d1ead61048c196653ba1f.tar.xz
arch-riscv: Move standard ops out of ISA
This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/insts')
-rw-r--r--src/arch/riscv/insts/SConscript1
-rw-r--r--src/arch/riscv/insts/bitfields.hh9
-rw-r--r--src/arch/riscv/insts/standard.cc67
-rw-r--r--src/arch/riscv/insts/standard.hh107
4 files changed, 184 insertions, 0 deletions
diff --git a/src/arch/riscv/insts/SConscript b/src/arch/riscv/insts/SConscript
index 95e6afd61..fe9028029 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,4 +1,5 @@
Import('*')
if env['TARGET_ISA'] == 'riscv':
+ Source('standard.cc')
Source('static_inst.cc') \ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh b/src/arch/riscv/insts/bitfields.hh
new file mode 100644
index 000000000..45744e081
--- /dev/null
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -0,0 +1,9 @@
+#ifndef __ARCH_RISCV_BITFIELDS_HH__
+#define __ARCH_RISCV_BITFIELDS_HH__
+
+#include "base/bitfield.hh"
+
+#define CSRIMM bits(machInst, 19, 15)
+#define FUNCT12 bits(machInst, 31, 20)
+
+#endif // __ARCH_RISCV_BITFIELDS_HH__ \ No newline at end of file
diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc
new file mode 100644
index 000000000..bcf0741f9
--- /dev/null
+++ b/src/arch/riscv/insts/standard.cc
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#include "arch/riscv/insts/standard.hh"
+
+#include <sstream>
+#include <string>
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+using namespace std;
+
+namespace RiscvISA
+{
+
+string
+RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ stringstream ss;
+ ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+ registerName(_srcRegIdx[0]) << ", " <<
+ registerName(_srcRegIdx[1]);
+ return ss.str();
+}
+
+string
+CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ stringstream ss;
+ ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
+ if (_numSrcRegs > 0)
+ ss << registerName(_srcRegIdx[0]) << ", ";
+ ss << MiscRegNames.at(csr);
+ return ss.str();
+}
+
+} \ No newline at end of file
diff --git a/src/arch/riscv/insts/standard.hh b/src/arch/riscv/insts/standard.hh
new file mode 100644
index 000000000..788bab240
--- /dev/null
+++ b/src/arch/riscv/insts/standard.hh
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_STANDARD_INST_HH__
+#define __ARCH_RISCV_STANDARD_INST_HH__
+
+#include <string>
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Base class for operations that work only on registers
+ */
+class RegOp : public RiscvStaticInst
+{
+ protected:
+ using RiscvStaticInst::RiscvStaticInst;
+
+ std::string generateDisassembly(
+ Addr pc, const SymbolTable *symtab) const override;
+};
+
+/**
+ * Base class for operations with immediates (I is the type of immediate)
+ */
+template<typename I>
+class ImmOp : public RiscvStaticInst
+{
+ protected:
+ I imm;
+
+ ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
+ {}
+};
+
+/**
+ * Base class for system operations
+ */
+class SystemOp : public RiscvStaticInst
+{
+ protected:
+ using RiscvStaticInst::RiscvStaticInst;
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const override
+ {
+ return mnemonic;
+ }
+};
+
+/**
+ * Base class for CSR operations
+ */
+class CSROp : public RiscvStaticInst
+{
+ protected:
+ uint64_t csr;
+ uint64_t uimm;
+
+ /// Constructor
+ CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass),
+ csr(FUNCT12), uimm(CSRIMM)
+ {}
+
+ std::string generateDisassembly(
+ Addr pc, const SymbolTable *symtab) const override;
+};
+
+}
+
+#endif // __ARCH_RISCV_STANDARD_INST_HH__ \ No newline at end of file