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authorAlec Roelke <ar4jc@virginia.edu>2017-03-21 12:54:50 -0400
committerAlec Roelke <ar4jc@virginia.edu>2017-04-05 20:21:45 +0000
commit616d48a570296f3d6eb38e5ce5e6fe41facf1a29 (patch)
tree62f4ae2782d9ff1c4f43ce3abcf190113ee0e8bb /src/arch/riscv/isa.cc
parentcd06bcf4ec2443eb719410e7e496e3d9d4d479c9 (diff)
downloadgem5-616d48a570296f3d6eb38e5ce5e6fe41facf1a29.tar.xz
riscv: add remote gdb support
This patch adds support for debugging with remote GDB to RISC-V. Using GDB compiled with the RISC-V GNU toolchain, it is possible to pause and continue execution, view debugging information, etc. As with the rest of RISC-V, this does not support full-system mode. Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d Reviewed-on: https://gem5-review.googlesource.com/2304 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/isa.cc')
-rw-r--r--src/arch/riscv/isa.cc194
1 files changed, 120 insertions, 74 deletions
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index c9505f5d7..d99954be4 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -32,6 +32,7 @@
#include <ctime>
#include <set>
+#include <sstream>
#include "arch/riscv/registers.hh"
#include "base/bitfield.hh"
@@ -44,79 +45,114 @@
namespace RiscvISA
{
-std::map<int, std::string> ISA::miscRegNames = {
- {MISCREG_FFLAGS, "fflags"},
- {MISCREG_FRM, "frm"},
- {MISCREG_FCSR, "fcsr"},
- {MISCREG_CYCLE, "cycle"},
- {MISCREG_TIME, "time"},
- {MISCREG_INSTRET, "instret"},
- {MISCREG_CYCLEH, "cycleh"},
- {MISCREG_TIMEH, "timeh"},
- {MISCREG_INSTRETH, "instreth"},
-
- {MISCREG_SSTATUS, "sstatus"},
- {MISCREG_STVEC, "stvec"},
- {MISCREG_SIE, "sie"},
- {MISCREG_STIMECMP, "stimecmp"},
- {MISCREG_STIME, "stime"},
- {MISCREG_STIMEH, "stimeh"},
- {MISCREG_SSCRATCH, "sscratch"},
- {MISCREG_SEPC, "sepc"},
- {MISCREG_SCAUSE, "scause"},
- {MISCREG_SBADADDR, "sbadaddr"},
- {MISCREG_SIP, "sip"},
- {MISCREG_SPTBR, "sptbr"},
- {MISCREG_SASID, "sasid"},
- {MISCREG_CYCLEW, "cyclew"},
- {MISCREG_TIMEW, "timew"},
- {MISCREG_INSTRETW, "instretw"},
- {MISCREG_CYCLEHW, "cyclehw"},
- {MISCREG_TIMEHW, "timehw"},
- {MISCREG_INSTRETHW, "instrethw"},
-
- {MISCREG_HSTATUS, "hstatus"},
- {MISCREG_HTVEC, "htvec"},
- {MISCREG_HTDELEG, "htdeleg"},
- {MISCREG_HTIMECMP, "htimecmp"},
- {MISCREG_HTIME, "htime"},
- {MISCREG_HTIMEH, "htimeh"},
- {MISCREG_HSCRATCH, "hscratch"},
- {MISCREG_HEPC, "hepc"},
- {MISCREG_HCAUSE, "hcause"},
- {MISCREG_HBADADDR, "hbadaddr"},
- {MISCREG_STIMEW, "stimew"},
- {MISCREG_STIMEHW, "stimehw"},
-
- {MISCREG_MCPUID, "mcpuid"},
- {MISCREG_MIMPID, "mimpid"},
- {MISCREG_MHARTID, "mhartid"},
- {MISCREG_MSTATUS, "mstatus"},
- {MISCREG_MTVEC, "mtvec"},
- {MISCREG_MTDELEG, "mtdeleg"},
- {MISCREG_MIE, "mie"},
- {MISCREG_MTIMECMP, "mtimecmp"},
- {MISCREG_MTIME, "mtime"},
- {MISCREG_MTIMEH, "mtimeh"},
- {MISCREG_MSCRATCH, "mscratch"},
- {MISCREG_MEPC, "mepc"},
- {MISCREG_MCAUSE, "mcause"},
- {MISCREG_MBADADDR, "mbadaddr"},
- {MISCREG_MIP, "mip"},
- {MISCREG_MBASE, "mbase"},
- {MISCREG_MBOUND, "mbound"},
- {MISCREG_MIBASE, "mibase"},
- {MISCREG_MIBOUND, "mibound"},
- {MISCREG_MDBASE, "mdbase"},
- {MISCREG_MDBOUND, "mdbound"},
- {MISCREG_HTIMEW, "htimew"},
- {MISCREG_HTIMEHW, "htimehw"},
- {MISCREG_MTOHOST, "mtohost"},
- {MISCREG_MFROMHOST, "mfromhost"}
-};
-
ISA::ISA(Params *p) : SimObject(p)
{
+ miscRegNames = {
+ {MISCREG_USTATUS, "ustatus"},
+ {MISCREG_UIE, "uie"},
+ {MISCREG_UTVEC, "utvec"},
+ {MISCREG_USCRATCH, "uscratch"},
+ {MISCREG_UEPC, "uepc"},
+ {MISCREG_UCAUSE, "ucause"},
+ {MISCREG_UBADADDR, "ubadaddr"},
+ {MISCREG_UIP, "uip"},
+ {MISCREG_FFLAGS, "fflags"},
+ {MISCREG_FRM, "frm"},
+ {MISCREG_FCSR, "fcsr"},
+ {MISCREG_CYCLE, "cycle"},
+ {MISCREG_TIME, "time"},
+ {MISCREG_INSTRET, "instret"},
+ {MISCREG_CYCLEH, "cycleh"},
+ {MISCREG_TIMEH, "timeh"},
+ {MISCREG_INSTRETH, "instreth"},
+
+ {MISCREG_SSTATUS, "sstatus"},
+ {MISCREG_SEDELEG, "sedeleg"},
+ {MISCREG_SIDELEG, "sideleg"},
+ {MISCREG_SIE, "sie"},
+ {MISCREG_STVEC, "stvec"},
+ {MISCREG_SSCRATCH, "sscratch"},
+ {MISCREG_SEPC, "sepc"},
+ {MISCREG_SCAUSE, "scause"},
+ {MISCREG_SBADADDR, "sbadaddr"},
+ {MISCREG_SIP, "sip"},
+ {MISCREG_SPTBR, "sptbr"},
+
+ {MISCREG_HSTATUS, "hstatus"},
+ {MISCREG_HEDELEG, "hedeleg"},
+ {MISCREG_HIDELEG, "hideleg"},
+ {MISCREG_HIE, "hie"},
+ {MISCREG_HTVEC, "htvec"},
+ {MISCREG_HSCRATCH, "hscratch"},
+ {MISCREG_HEPC, "hepc"},
+ {MISCREG_HCAUSE, "hcause"},
+ {MISCREG_HBADADDR, "hbadaddr"},
+ {MISCREG_HIP, "hip"},
+
+ {MISCREG_MVENDORID, "mvendorid"},
+ {MISCREG_MARCHID, "marchid"},
+ {MISCREG_MIMPID, "mimpid"},
+ {MISCREG_MHARTID, "mhartid"},
+ {MISCREG_MSTATUS, "mstatus"},
+ {MISCREG_MISA, "misa"},
+ {MISCREG_MEDELEG, "medeleg"},
+ {MISCREG_MIDELEG, "mideleg"},
+ {MISCREG_MIE, "mie"},
+ {MISCREG_MTVEC, "mtvec"},
+ {MISCREG_MSCRATCH, "mscratch"},
+ {MISCREG_MEPC, "mepc"},
+ {MISCREG_MCAUSE, "mcause"},
+ {MISCREG_MBADADDR, "mbadaddr"},
+ {MISCREG_MIP, "mip"},
+ {MISCREG_MBASE, "mbase"},
+ {MISCREG_MBOUND, "mbound"},
+ {MISCREG_MIBASE, "mibase"},
+ {MISCREG_MIBOUND, "mibound"},
+ {MISCREG_MDBASE, "mdbase"},
+ {MISCREG_MDBOUND, "mdbound"},
+ {MISCREG_MCYCLE, "mcycle"},
+ {MISCREG_MINSTRET, "minstret"},
+ {MISCREG_MUCOUNTEREN, "mucounteren"},
+ {MISCREG_MSCOUNTEREN, "mscounteren"},
+ {MISCREG_MHCOUNTEREN, "mhcounteren"},
+
+ {MISCREG_TSELECT, "tselect"},
+ {MISCREG_TDATA1, "tdata1"},
+ {MISCREG_TDATA2, "tdata2"},
+ {MISCREG_TDATA3, "tdata3"},
+ {MISCREG_DCSR, "dcsr"},
+ {MISCREG_DPC, "dpc"},
+ {MISCREG_DSCRATCH, "dscratch"}
+ };
+ for (int i = 0; i < NumHpmcounter; i++)
+ {
+ int hpmcounter = MISCREG_HPMCOUNTER_BASE + i;
+ std::stringstream ss;
+ ss << "hpmcounter" << hpmcounter;
+ miscRegNames[hpmcounter] = ss.str();
+ }
+ for (int i = 0; i < NumHpmcounterh; i++)
+ {
+ int hpmcounterh = MISCREG_HPMCOUNTERH_BASE + i;
+ std::stringstream ss;
+ ss << "hpmcounterh" << hpmcounterh;
+ miscRegNames[hpmcounterh] = ss.str();
+ }
+ for (int i = 0; i < NumMhpmcounter; i++)
+ {
+ int mhpmcounter = MISCREG_MHPMCOUNTER_BASE + i;
+ std::stringstream ss;
+ ss << "mhpmcounter" << mhpmcounter;
+ miscRegNames[mhpmcounter] = ss.str();
+ }
+ for (int i = 0; i < NumMhpmevent; i++)
+ {
+ int mhpmevent = MISCREG_MHPMEVENT_BASE + i;
+ std::stringstream ss;
+ ss << "mhpmcounterh" << mhpmevent;
+ miscRegNames[mhpmevent] = ss.str();
+ }
+
miscRegFile.resize(NumMiscRegs);
clear();
}
@@ -130,14 +166,19 @@ ISA::params() const
void ISA::clear()
{
std::fill(miscRegFile.begin(), miscRegFile.end(), 0);
+
+ miscRegFile[MISCREG_MVENDORID] = 0;
+ miscRegFile[MISCREG_MARCHID] = 0;
+ miscRegFile[MISCREG_MIMPID] = 0;
+ miscRegFile[MISCREG_MISA] = 0x8000000000101129ULL;
}
MiscReg
ISA::readMiscRegNoEffect(int misc_reg) const
{
- DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n", miscRegNames[misc_reg],
- miscRegFile[misc_reg]);
+ DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
+ miscRegNames.at(misc_reg), miscRegFile[misc_reg]);
switch (misc_reg) {
case MISCREG_FFLAGS:
return bits(miscRegFile[MISCREG_FCSR], 4, 0);
@@ -161,6 +202,9 @@ ISA::readMiscRegNoEffect(int misc_reg) const
case MISCREG_INSTRETH:
warn("Use readMiscReg to read the instreth CSR.");
return 0;
+ case MISCREG_MHARTID:
+ warn("Use readMiscReg to read the mhartid CSR.");
+ return 0;
default:
return miscRegFile[misc_reg];
}
@@ -186,6 +230,8 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
DPRINTF(RiscvMisc, "Reading CSR %s (0x%016llx).\n",
miscRegNames[misc_reg], miscRegFile[misc_reg]);
return tc->getCpuPtr()->curCycle() >> 32;
+ case MISCREG_MHARTID:
+ return 0; // TODO: make this the hardware thread or cpu id
default:
return readMiscRegNoEffect(misc_reg);
}
@@ -195,7 +241,7 @@ void
ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
DPRINTF(RiscvMisc, "Setting CSR %s to 0x%016llx.\n",
- miscRegNames[misc_reg], miscRegNames[misc_reg], val);
+ miscRegNames[misc_reg], val);
switch (misc_reg) {
case MISCREG_FFLAGS:
miscRegFile[MISCREG_FCSR] &= ~0x1F;