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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-11-07 14:15:41 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-11-29 00:55:46 +0000 |
| commit | eb02066b31c85d22c67d1ead61048c196653ba1f (patch) | |
| tree | 1ab43820091dcf702bf2e7ed083eb27bd3cfb313 /src/arch/riscv/isa/formats/compressed.isa | |
| parent | d3ecb5d406a3dc12c53a20c271db3027b8477c39 (diff) | |
| download | gem5-eb02066b31c85d22c67d1ead61048c196653ba1f.tar.xz | |
arch-riscv: Move standard ops out of ISA
This patch removes static portions of the standard instruction types
from the generated ISA code and puts them into arch/riscv/insts. Some
dynamically-generated content is left behind for each individual
instruction's implementation. Also, BranchOp is removed due to its
similarity with ImmOp and ImmOp and UImmOp are joined into a single
templated class, ImmOp<T>.
Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
Reviewed-on: https://gem5-review.googlesource.com/6022
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/isa/formats/compressed.isa')
| -rw-r--r-- | src/arch/riscv/isa/formats/compressed.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa index 1fd2319fd..683795d89 100644 --- a/src/arch/riscv/isa/formats/compressed.isa +++ b/src/arch/riscv/isa/formats/compressed.isa @@ -67,7 +67,7 @@ def format CROp(code, *opt_flags) {{ def format CIOp(imm_code, code, *opt_flags) {{ regs = ['_destRegIdx[0]','_srcRegIdx[0]'] - iop = InstObjParams(name, Name, 'ImmOp', + iop = InstObjParams(name, Name, 'ImmOp<int64_t>', {'code': code, 'imm_code': imm_code, 'regs': ','.join(regs)}, opt_flags) header_output = ImmDeclare.subst(iop) @@ -78,7 +78,7 @@ def format CIOp(imm_code, code, *opt_flags) {{ def format CUIOp(imm_code, code, *opt_flags) {{ regs = ['_destRegIdx[0]','_srcRegIdx[0]'] - iop = InstObjParams(name, Name, 'UImmOp', + iop = InstObjParams(name, Name, 'ImmOp<uint64_t>', {'code': code, 'imm_code': imm_code, 'regs': ','.join(regs)}, opt_flags) header_output = ImmDeclare.subst(iop) |