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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-11-07 15:19:56 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-11-29 00:58:23 +0000 |
| commit | 719ddf73afa62735881ac68acf681abe1bf3bd17 (patch) | |
| tree | 71ba0ac50a066504c9df48cde18ba65f2da05689 /src/arch/riscv/isa/formats/mem.isa | |
| parent | 19ad3c4ae46426e988602d870dc2c27fee1154f1 (diff) | |
| download | gem5-719ddf73afa62735881ac68acf681abe1bf3bd17.tar.xz | |
arch-riscv: Move parts of mem insts out of ISA
This patch moves static portions of the memory instructions out of the
ISA generated code and puts them into arch/riscv/insts. It also
simplifies the definitions of load and store instructions by giving
them a common base class.
Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803
Reviewed-on: https://gem5-review.googlesource.com/6024
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/isa/formats/mem.isa')
| -rw-r--r-- | src/arch/riscv/isa/formats/mem.isa | 78 |
1 files changed, 6 insertions, 72 deletions
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index bce76c4d5..ef5f9527c 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -33,72 +33,6 @@ // // Memory operation instructions // -output header {{ - class Load : public RiscvStaticInst - { - public: - /// Displacement for EA calculation (signed). - int64_t ldisp; - - protected: - /// Memory request flags. See mem_req_base.hh. - Request::Flags memAccessFlags; - - /// Constructor - Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : RiscvStaticInst(mnem, _machInst, __opClass), ldisp(0) - {} - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - - class Store : public RiscvStaticInst - { - public: - /// Displacement for EA calculation (signed). - int64_t sdisp; - - protected: - /// Memory request flags. See mem_req_base.hh. - Request::Flags memAccessFlags; - - /// Constructor - Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : RiscvStaticInst(mnem, _machInst, __opClass), sdisp(0) - { - sdisp = IMM5 | (IMM7 << 5); - if (IMMSIGN > 0) - sdisp |= ~((uint64_t)0xFFF); - } - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - -}}; - - -output decoder {{ - std::string - Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " << - ldisp << '(' << registerName(_srcRegIdx[0]) << ')'; - return ss.str(); - } - - std::string - Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - ss << mnemonic << ' ' << registerName(_srcRegIdx[1]) << ", " << - sdisp << '(' << registerName(_srcRegIdx[0]) << ')'; - return ss.str(); - } -}}; - def template LoadStoreDeclare {{ /** * Static instruction class for "%(mnemonic)s". @@ -320,24 +254,24 @@ def template StoreCompleteAcc {{ } }}; -def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[], +def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}}, mem_flags=[], inst_flags=[]) {{ offset_code = """ - ldisp = IMM12; + offset = IMM12; if (IMMSIGN > 0) - ldisp |= ~((uint64_t)0xFFF); + offset |= ~((uint64_t)0xFFF); """ (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags, inst_flags, 'Load', exec_template_base='Load') }}; -def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[], +def format Store(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[], inst_flags=[]) {{ offset_code = """ - sdisp = IMM5 | (IMM7 << 5); + offset = IMM5 | (IMM7 << 5); if (IMMSIGN > 0) - sdisp |= ~((uint64_t)0xFFF); + offset |= ~((uint64_t)0xFFF); """ (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags, |