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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-11-29 14:04:11 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-11-30 03:58:49 +0000 |
| commit | 937ed3a0a26002bc5e015c23ecd805e4e32b2cca (patch) | |
| tree | 51187af69c471a7ca82f5e94f142ef18fd507577 /src/arch/riscv/isa/formats/standard.isa | |
| parent | aed69fec188b8789675a4d3d1a712b42d4cf4f75 (diff) | |
| download | gem5-937ed3a0a26002bc5e015c23ecd805e4e32b2cca.tar.xz | |
arch-riscv: use sext rather than manual masks
Replace manual creation of masks for sign extension of immediates with
the sext<N> function.
Change-Id: Ief2df91a25500c64f5bcae0dcd437c1e3bb95e6c
Reviewed-on: https://gem5-review.googlesource.com/6182
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/isa/formats/standard.isa')
| -rw-r--r-- | src/arch/riscv/isa/formats/standard.isa | 31 |
1 files changed, 14 insertions, 17 deletions
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index e68cedfe2..517313d70 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -219,10 +219,9 @@ def format ROp(code, *opt_flags) {{ }}; def format IOp(code, *opt_flags) {{ - imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);' regs = ['_destRegIdx[0]','_srcRegIdx[0]'] iop = InstObjParams(name, Name, 'ImmOp<int64_t>', - {'code': code, 'imm_code': imm_code, + {'code': code, 'imm_code': 'imm = sext<12>(IMM12);', 'regs': ','.join(regs)}, opt_flags) header_output = ImmDeclare.subst(iop) decoder_output = ImmConstructor.subst(iop) @@ -232,11 +231,11 @@ def format IOp(code, *opt_flags) {{ def format BOp(code, *opt_flags) {{ imm_code = """ - imm |= BIMM12BIT11 << 11; - imm |= BIMM12BITS4TO1 << 1; - imm |= BIMM12BITS10TO5 << 5; - if (IMMSIGN > 0) - imm |= ~((uint64_t)0xFFF); + imm = BIMM12BITS4TO1 << 1 | + BIMM12BITS10TO5 << 5 | + BIMM12BIT11 << 11 | + IMMSIGN << 12; + imm = sext<13>(imm); """ regs = ['_srcRegIdx[0]','_srcRegIdx[1]'] iop = InstObjParams(name, Name, 'ImmOp<int64_t>', @@ -249,10 +248,9 @@ def format BOp(code, *opt_flags) {{ }}; def format Jump(code, *opt_flags) {{ - imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);' - regs = ['_destRegIdx[0]','_srcRegIdx[0]'] + regs = ['_destRegIdx[0]', '_srcRegIdx[0]'] iop = InstObjParams(name, Name, 'ImmOp<int64_t>', - {'code': code, 'imm_code': imm_code, + {'code': code, 'imm_code': 'imm = sext<12>(IMM12);', 'regs': ','.join(regs)}, opt_flags) header_output = JumpDeclare.subst(iop) decoder_output = ImmConstructor.subst(iop) @@ -261,10 +259,9 @@ def format Jump(code, *opt_flags) {{ }}; def format UOp(code, *opt_flags) {{ - imm_code = 'imm = (int32_t)(IMM20 << 12);' regs = ['_destRegIdx[0]'] iop = InstObjParams(name, Name, 'ImmOp<int64_t>', - {'code': code, 'imm_code': imm_code, + {'code': code, 'imm_code': 'imm = sext<20>(IMM20) << 12;', 'regs': ','.join(regs)}, opt_flags) header_output = ImmDeclare.subst(iop) decoder_output = ImmConstructor.subst(iop) @@ -274,11 +271,11 @@ def format UOp(code, *opt_flags) {{ def format JOp(code, *opt_flags) {{ imm_code = """ - imm |= UJIMMBITS19TO12 << 12; - imm |= UJIMMBIT11 << 11; - imm |= UJIMMBITS10TO1 << 1; - if (IMMSIGN > 0) - imm |= ~((uint64_t)0xFFFFF); + imm = UJIMMBITS10TO1 << 1 | + UJIMMBIT11 << 11 | + UJIMMBITS19TO12 << 12 | + IMMSIGN << 20; + imm = sext<21>(imm); """ pc = 'pc.set(pc.pc() + imm);' regs = ['_destRegIdx[0]'] |