arch-riscv: Add support for compressed extension RV64C

This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C.  Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).

[Update diassembly generation for new RegId type.]
[Rebase onto master.]

Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Reviewed-on: https://gem5-review.googlesource.com/3860
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

3 files changed, 131 insertions, 17 deletions

diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa
new file mode 100644
index 000000000..1fd2319fd
--- /dev/null
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -0,0 +1,102 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2017 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Alec Roelke
+
+output header {{
+    /**
+     * Base class for compressed operations that work only on registers
+     */
+    class CompRegOp : public RiscvStaticInst
+    {
+      protected:
+        /// Constructor
+        CompRegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : RiscvStaticInst(mnem, _machInst, __opClass)
+        {}
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+}};
+
+output decoder {{
+    std::string
+    CompRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+        ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+            registerName(_srcRegIdx[0]);
+        return ss.str();
+    }
+}};
+
+def format CROp(code, *opt_flags) {{
+    iop = InstObjParams(name, Name, 'CompRegOp', code, opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format CIOp(imm_code, code, *opt_flags) {{
+    regs = ['_destRegIdx[0]','_srcRegIdx[0]']
+    iop = InstObjParams(name, Name, 'ImmOp',
+        {'code': code, 'imm_code': imm_code,
+         'regs': ','.join(regs)}, opt_flags)
+    header_output = ImmDeclare.subst(iop)
+    decoder_output = ImmConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = ImmExecute.subst(iop)
+}};
+
+def format CUIOp(imm_code, code, *opt_flags) {{
+    regs = ['_destRegIdx[0]','_srcRegIdx[0]']
+    iop = InstObjParams(name, Name, 'UImmOp',
+        {'code': code, 'imm_code': imm_code,
+         'regs': ','.join(regs)}, opt_flags)
+    header_output = ImmDeclare.subst(iop)
+    decoder_output = ImmConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = ImmExecute.subst(iop)
+}};
+
+def format CompressedLoad(ldisp_code, memacc_code,
+        ea_code, mem_flags=[], inst_flags=[]) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ldisp_code, ea_code, memacc_code, mem_flags,
+        inst_flags, 'Load', exec_template_base='Load')
+}};
+
+def format CompressedStore(sdisp_code, memacc_code,
+        ea_code, mem_flags=[], inst_flags=[]) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags,
+        inst_flags, 'Store', exec_template_base='Store')
+}};
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/formats.isa b/src/arch/riscv/isa/formats/formats.isa
index e13cac263..df2b3b84a 100644
--- a/src/arch/riscv/isa/formats/formats.isa
+++ b/src/arch/riscv/isa/formats/formats.isa
@@ -33,11 +33,14 @@
 // Include the basic format
 ##include "basic.isa"
 
-//Include the type formats
+// Include the type formats
 ##include "standard.isa"
 ##include "mem.isa"
 ##include "fp.isa"
 ##include "amo.isa"
 
+// Include formats for nonstandard extensions
+##include "compressed.isa"
+
 // Include the unknown
 ##include "unknown.isa"
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa
index 4ae8eb41a..9b6bc9eb5 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -46,11 +46,8 @@ output header {{
 
         /// Constructor
         Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
-            : RiscvStaticInst(mnem, _machInst, __opClass), ldisp(IMM12)
-        {
-            if (IMMSIGN > 0)
-                ldisp |= ~((uint64_t)0xFFF);
-        }
+            : RiscvStaticInst(mnem, _machInst, __opClass), ldisp(0)
+        {}
 
         std::string
         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -68,9 +65,9 @@ output header {{
 
         /// Constructor
         Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
-            : RiscvStaticInst(mnem, _machInst, __opClass), sdisp(IMM5)
+            : RiscvStaticInst(mnem, _machInst, __opClass), sdisp(0)
         {
-            sdisp |= IMM7 << 5;
+            sdisp = IMM5 | (IMM7 << 5);
             if (IMMSIGN > 0)
                 sdisp |= ~((uint64_t)0xFFF);
         }
@@ -143,6 +140,7 @@ def template LoadStoreConstructor {{
         %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
     {
         %(constructor)s;
+        %(offset_code)s;
     }
 }};
 
@@ -168,16 +166,17 @@ def template EACompExecute {{
 }};
 
 let {{
-def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-        base_class, postacc_code='', decode_template=BasicDecode,
+def LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
+        inst_flags, base_class, postacc_code='', decode_template=BasicDecode,
         exec_template_base=''):
     # Make sure flags are in lists (convert to lists if not).
     mem_flags = makeList(mem_flags)
-    inst_flags = makeList(inst_flags) # + ['IsNonSpeculative']
+    inst_flags = makeList(inst_flags)
 
     iop = InstObjParams(name, Name, base_class,
-        { 'ea_code':ea_code, 'memacc_code':memacc_code,
-        'postacc_code':postacc_code }, inst_flags)
+        {'offset_code': offset_code, 'ea_code': ea_code,
+         'memacc_code': memacc_code, 'postacc_code': postacc_code },
+        inst_flags)
 
     if mem_flags:
         mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
@@ -342,14 +341,24 @@ def template StoreCompleteAcc {{
 
 def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
         inst_flags=[]) {{
+    offset_code = """
+                    ldisp = IMM12;
+                    if (IMMSIGN > 0)
+                        ldisp |= ~((uint64_t)0xFFF);
+                  """
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-        'Load', exec_template_base='Load')
+        LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
+        inst_flags, 'Load', exec_template_base='Load')
 }};
 
 def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
         inst_flags=[]) {{
+    offset_code = """
+                    sdisp = IMM5 | (IMM7 << 5);
+                    if (IMMSIGN > 0)
+                        sdisp |= ~((uint64_t)0xFFF);
+                  """
     (header_output, decoder_output, decode_block, exec_output) = \
-        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
-        'Store', exec_template_base='Store')
+        LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
+        inst_flags, 'Store', exec_template_base='Store')
 }};