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author | Alec Roelke <ar4jc@virginia.edu> | 2017-11-10 12:23:43 -0500 |
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committer | Alec Roelke <ar4jc@virginia.edu> | 2017-11-29 01:05:24 +0000 |
commit | 3f31abfbc84734dab86734c72bdca778575c26e5 (patch) | |
tree | ab5e7c74b35c90c43c79cd5d40ba1f2751bbd05a /src/arch/riscv/isa/formats | |
parent | 719ddf73afa62735881ac68acf681abe1bf3bd17 (diff) | |
download | gem5-3f31abfbc84734dab86734c72bdca778575c26e5.tar.xz |
arch-riscv: Remove static parts of AMOs out of ISA
This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.
Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
Reviewed-on: https://gem5-review.googlesource.com/6025
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/isa/formats')
-rw-r--r-- | src/arch/riscv/isa/formats/amo.isa | 97 |
1 files changed, 0 insertions, 97 deletions
diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa index 80a5faa19..ea4e14885 100644 --- a/src/arch/riscv/isa/formats/amo.isa +++ b/src/arch/riscv/isa/formats/amo.isa @@ -33,103 +33,6 @@ // // Atomic memory operation instructions // -output header {{ - class LoadReserved : public RiscvStaticInst - { - protected: - Request::Flags memAccessFlags; - - LoadReserved(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : RiscvStaticInst(mnem, _machInst, __opClass) - {} - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - - class StoreCond : public RiscvStaticInst - { - protected: - Request::Flags memAccessFlags; - - StoreCond(const char* mnem, ExtMachInst _machInst, OpClass __opClass) - : RiscvStaticInst(mnem, _machInst, __opClass) - {} - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - - class AtomicMemOp : public RiscvMacroInst - { - protected: - /// Constructor - // Each AtomicMemOp has a load and a store phase - AtomicMemOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : RiscvMacroInst(mnem, _machInst, __opClass) - {} - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - }; - - class AtomicMemOpMicro : public RiscvMicroInst - { - protected: - /// Memory request flags. See mem/request.hh. - Request::Flags memAccessFlags; - - /// Constructor - AtomicMemOpMicro(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : RiscvMicroInst(mnem, _machInst, __opClass) - {} - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string LoadReserved::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream ss; - ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", (" - << registerName(_srcRegIdx[0]) << ')'; - return ss.str(); - } - - std::string StoreCond::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream ss; - ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " - << registerName(_srcRegIdx[1]) << ", (" - << registerName(_srcRegIdx[0]) << ')'; - return ss.str(); - } - - std::string AtomicMemOp::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream ss; - ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " - << registerName(_srcRegIdx[1]) << ", (" - << registerName(_srcRegIdx[0]) << ')'; - return ss.str(); - } - - std::string AtomicMemOpMicro::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream ss; - ss << csprintf("0x%08x", machInst) << ' ' << mnemonic; - return ss.str(); - } -}}; - def template AtomicMemOpDeclare {{ /** * Static instruction class for an AtomicMemOp operation |