riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A
extension, which includes atomic memory instructions. These instructions
atomically read a value from memory, modify it with a value contained in a
source register, and store the original memory value in the destination
register and modified value back into memory. Because this requires two
memory accesses and GEM5 does not support two timing memory accesses in
a single instruction, each of these instructions is split into two micro-
ops: A "load" micro-op, which reads the memory, and a "store" micro-op,
which modifies and writes it back.  Each atomic memory instruction also has
two bits that acquire and release a lock on its memory location.
Additionally, there are atomic load and store instructions that only either
load or store, but not both, and can acquire or release memory locks.

Note that because the current implementation of RISC-V only supports one
core and one thread, it doesn't make sense to make use of AMO instructions.
However, they do form a standard extension of the RISC-V ISA, so they are
included mostly as a placeholder for when multithreaded execution is
implemented.  As a result, any tests for their correctness in a future
patch may be abbreviated.

Patch 1 introduced RISC-V and implemented the base instruction set, RV64I;
patch 2 implemented the integer multiply extension, RV64M; and patch 3
implemented the single- and double-precision floating point extensions,
RV64FD.

Patch 5 will add support for timing, minor, and detailed CPU models that
isn't present in patches 1-4.

[Added missing file amo.isa]
[Replaced information removed from initial patch that was missed during
division into multiple patches.]
[Fixed some minor formatting issues.]
[Fixed oversight where LR and SC didn't have both AQ and RL flags.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 115 insertions, 0 deletions

diff --git a/src/arch/riscv/isa/micro.isa b/src/arch/riscv/isa/micro.isa
new file mode 100644
index 000000000..bd9102d61
--- /dev/null
+++ b/src/arch/riscv/isa/micro.isa
@@ -0,0 +1,115 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 Riscv Developers
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Alec Roelke
+
+def template MacroInitiateAcc {{
+    Fault initiateAcc(%(CPU_exec_context)s *xc,
+        Trace::InstRecord *traceData) const
+    {
+        panic("Tried to execute a macroop directly!\n");
+        return NoFault;
+    }
+}};
+
+def template MacroCompleteAcc {{
+    Fault completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc,
+        Trace::InstRecord *traceData) const
+    {
+        panic("Tried to execute a macroop directly!\n");
+        return NoFault;
+    }
+}};
+
+def template MacroExecute {{
+    Fault execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+    {
+        panic("Tried to execute a macroop directly!\n");
+        return NoFault;
+    }
+}};
+
+output header {{
+    /**
+     * Base class for all RISC-V Macroops
+     */
+    class RiscvMacroInst : public RiscvStaticInst
+    {
+    protected:
+        std::vector<StaticInstPtr> microops;
+
+        // Constructor
+        RiscvMacroInst(const char *mnem, ExtMachInst _machInst,
+            OpClass __opClass)
+                : RiscvStaticInst(mnem, _machInst, __opClass)
+        {
+            flags[IsMacroop] = true;
+        }
+
+        ~RiscvMacroInst()
+        {
+            microops.clear();
+        }
+
+        StaticInstPtr fetchMicroop(MicroPC upc) const
+        {
+            return microops[upc];
+        }
+
+        %(MacroInitiateAcc)s
+
+        %(MacroCompleteAcc)s
+
+        %(MacroExecute)s
+    };
+
+    /**
+     * Base class for all RISC-V Microops
+     */
+    class RiscvMicroInst : public RiscvStaticInst
+    {
+    protected:
+        // Constructor
+        RiscvMicroInst(const char *mnem, ExtMachInst _machInst,
+            OpClass __opClass)
+                : RiscvStaticInst(mnem, _machInst, __opClass)
+        {
+            flags[IsMicroop] = true;
+        }
+
+        void advancePC(RiscvISA::PCState &pcState) const
+        {
+            if (flags[IsLastMicroop]) {
+                pcState.uEnd();
+            } else {
+                pcState.uAdvance();
+            }
+        }
+    };
+}};