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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-06-14 17:33:29 -0400 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-07-11 03:45:14 +0000 |
| commit | 7e6a35374a944b67868d92ce85b427ea9103ca53 (patch) | |
| tree | 0fe3c97c11967468b2c66ce0edbc656d3c485a61 /src/arch/riscv/isa/operands.isa | |
| parent | 63d4005a29dea37e0219444a3de2cdb25289fdfb (diff) | |
| download | gem5-7e6a35374a944b67868d92ce85b427ea9103ca53.tar.xz | |
arch-riscv: Add support for compressed extension RV64C
This patch adds compatibility with the 64-bit compressed extension to
the RISC-V ISA, RV64C. Current versions of the toolchain may use
compressed instructions in glibc by default, which can only be
overridden by recompiling the entire toolchain (simply adding
"-march=rv64g" or "-march=rv64imafd" when compiling a binary is not
sufficient to use uncompressed instructions in glibc functions in the
binary).
[Update diassembly generation for new RegId type.]
[Rebase onto master.]
Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4
Reviewed-on: https://gem5-review.googlesource.com/3860
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/isa/operands.isa')
| -rw-r--r-- | src/arch/riscv/isa/operands.isa | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/riscv/isa/operands.isa b/src/arch/riscv/isa/operands.isa index 7a8385d0c..8dc1a3b82 100644 --- a/src/arch/riscv/isa/operands.isa +++ b/src/arch/riscv/isa/operands.isa @@ -49,6 +49,12 @@ def operands {{ 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2), 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3), 'Rt': ('IntReg', 'ud', 'AMOTempReg', 'IsInteger', 4), + 'Rc1': ('IntReg', 'ud', 'RC1', 'IsInteger', 2), + 'Rc2': ('IntReg', 'ud', 'RC2', 'IsInteger', 3), + 'Rp1': ('IntReg', 'ud', 'RP1 + 8', 'IsInteger', 2), + 'Rp2': ('IntReg', 'ud', 'RP2 + 8', 'IsInteger', 3), + 'ra': ('IntReg', 'ud', 'ReturnAddrReg', 'IsInteger', 1), + 'sp': ('IntReg', 'ud', 'StackPointerReg', 'IsInteger', 2), 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1), 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1), @@ -58,6 +64,12 @@ def operands {{ 'Fs2_bits': ('FloatReg', 'ud', 'FS2', 'IsFloating', 3), 'Fs3': ('FloatReg', 'df', 'FS3', 'IsFloating', 4), 'Fs3_bits': ('FloatReg', 'ud', 'FS3', 'IsFloating', 4), + 'Fc1': ('FloatReg', 'df', 'FC1', 'IsFloating', 1), + 'Fc1_bits': ('FloatReg', 'ud', 'FC1', 'IsFloating', 1), + 'Fc2': ('FloatReg', 'df', 'FC2', 'IsFloatReg', 2), + 'Fc2_bits': ('FloatReg', 'ud', 'FC2', 'IsFloating', 2), + 'Fp2': ('FloatReg', 'df', 'FP2 + 8', 'IsFloating', 2), + 'Fp2_bits': ('FloatReg', 'ud', 'FP2 + 8', 'IsFloating', 2), #Memory Operand 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5), |