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| author | Alec Roelke <ar4jc@virginia.edu> | 2017-11-07 12:11:11 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-11-29 00:57:23 +0000 |
| commit | 19ad3c4ae46426e988602d870dc2c27fee1154f1 (patch) | |
| tree | e9507c51086e8c2f9f5f250f899d5dcb47e20a95 /src/arch/riscv/isa | |
| parent | eb02066b31c85d22c67d1ead61048c196653ba1f (diff) | |
| download | gem5-19ad3c4ae46426e988602d870dc2c27fee1154f1.tar.xz | |
arch-riscv: Move unknown out of ISA description
This patch removes the Unknown instruction type out of the ISA generated
code and puts it into arch/riscv/insts. Since there isn't any dynamic
behavior to it, all that's left behind is a template for creating a new
Unknown instruction.
Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db
Reviewed-on: https://gem5-review.googlesource.com/6023
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/isa')
| -rw-r--r-- | src/arch/riscv/isa/formats/unknown.isa | 41 | ||||
| -rw-r--r-- | src/arch/riscv/isa/includes.isa | 1 |
2 files changed, 1 insertions, 41 deletions
diff --git a/src/arch/riscv/isa/formats/unknown.isa b/src/arch/riscv/isa/formats/unknown.isa index b6d76497d..7c2317f98 100644 --- a/src/arch/riscv/isa/formats/unknown.isa +++ b/src/arch/riscv/isa/formats/unknown.isa @@ -34,47 +34,6 @@ // // Unknown instructions // - -output header {{ - /** - * Static instruction class for unknown (illegal) instructions. - * These cause simulator termination if they are executed in a - * non-speculative mode. This is a leaf class. - */ - class Unknown : public RiscvStaticInst - { - public: - /// Constructor - Unknown(MachInst _machInst) - : RiscvStaticInst("unknown", _machInst, No_OpClass) - { - flags[IsNonSpeculative] = true; - } - - Fault execute(ExecContext *, Trace::InstRecord *) const; - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string - Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return csprintf("unknown opcode 0x%02x", OPCODE); - } -}}; - -output exec {{ - Fault - Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const - { - Fault fault = std::make_shared<UnknownInstFault>(); - return fault; - } -}}; - def format Unknown() {{ decode_block = 'return new Unknown(machInst);\n' }}; diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index dfd0f37b4..cd43996e8 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -44,6 +44,7 @@ output header {{ #include "arch/riscv/insts/standard.hh" #include "arch/riscv/insts/static_inst.hh" +#include "arch/riscv/insts/unknown.hh" #include "cpu/static_inst.hh" #include "mem/packet.hh" #include "mem/request.hh" |