summaryrefslogtreecommitdiff
path: root/src/arch/riscv/isa
diff options
context:
space:
mode:
authorGabe Black <gabeblack@google.com>2017-11-02 01:58:38 -0700
committerGabe Black <gabeblack@google.com>2017-11-02 09:43:35 +0000
commit8be75f49fd37712e7cf04c0853bb7504f69a04d6 (patch)
treef791cd8adccee52d054f5a10b62948021a3d121b /src/arch/riscv/isa
parent97c68e8fc56baa39ce7901ac1f73d2ff79b550f2 (diff)
downloadgem5-8be75f49fd37712e7cf04c0853bb7504f69a04d6.tar.xz
alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.
The ISA parser used to generate different copies of exec functions for each exec context class a particular CPU wanted to use. That's since been changed so that those functions take a pointer to the base ExecContext, so the code which would generate those extra functions can be removed, and some functions which used to be templated on an ExecContext subclass can be untemplated, or minimally less templated. Now that some functions aren't going to be instantiated multiple times with different signatures, there are also opportunities to collapse templates and make many instruction definitions simpler within the parser. Since those changes will be less mechanical, they're left for later changes and will probably be done in smaller increments. Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea Reviewed-on: https://gem5-review.googlesource.com/5381 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/riscv/isa')
-rw-r--r--src/arch/riscv/isa/formats/amo.isa18
-rw-r--r--src/arch/riscv/isa/formats/basic.isa4
-rw-r--r--src/arch/riscv/isa/formats/fp.isa2
-rw-r--r--src/arch/riscv/isa/formats/mem.isa23
-rw-r--r--src/arch/riscv/isa/formats/standard.isa12
-rw-r--r--src/arch/riscv/isa/formats/unknown.isa2
-rw-r--r--src/arch/riscv/isa/micro.isa7
7 files changed, 33 insertions, 35 deletions
diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa
index 24e13c984..983c1f4cc 100644
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -223,7 +223,7 @@ def template AtomicMemOpStoreConstructor {{
}};
def template StoreCondExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -259,7 +259,7 @@ def template StoreCondExecute {{
}};
def template AtomicMemOpLoadExecute {{
- Fault %(class_name)s::%(class_name)sLoad::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::%(class_name)sLoad::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -286,7 +286,7 @@ def template AtomicMemOpLoadExecute {{
}};
def template AtomicMemOpStoreExecute {{
- Fault %(class_name)s::%(class_name)sStore::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::%(class_name)sStore::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -315,7 +315,7 @@ def template AtomicMemOpStoreExecute {{
def template AtomicMemOpEACompExecute {{
Fault
- %(class_name)s::%(class_name)s%(op_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::%(class_name)s%(op_name)s::eaComp(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -335,7 +335,7 @@ def template AtomicMemOpEACompExecute {{
}};
def template AtomicMemOpLoadInitiateAcc {{
- Fault %(class_name)s::%(class_name)sLoad::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::%(class_name)sLoad::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -355,7 +355,7 @@ def template AtomicMemOpLoadInitiateAcc {{
def template AtomicMemOpStoreInitiateAcc {{
Fault %(class_name)s::%(class_name)sStore::initiateAcc(
- CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -382,7 +382,7 @@ def template AtomicMemOpStoreInitiateAcc {{
}};
def template StoreCondCompleteAcc {{
- Fault %(class_name)s::completeAcc(Packet *pkt, CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -407,7 +407,7 @@ def template StoreCondCompleteAcc {{
def template AtomicMemOpLoadCompleteAcc {{
Fault %(class_name)s::%(class_name)sLoad::completeAcc(PacketPtr pkt,
- CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -430,7 +430,7 @@ def template AtomicMemOpLoadCompleteAcc {{
def template AtomicMemOpStoreCompleteAcc {{
Fault %(class_name)s::%(class_name)sStore::completeAcc(PacketPtr pkt,
- CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
return NoFault;
}
diff --git a/src/arch/riscv/isa/formats/basic.isa b/src/arch/riscv/isa/formats/basic.isa
index 4126fcdd4..2d27fd8b5 100644
--- a/src/arch/riscv/isa/formats/basic.isa
+++ b/src/arch/riscv/isa/formats/basic.isa
@@ -32,7 +32,7 @@
// Declarations for execute() methods.
def template BasicExecDeclare {{
- Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
}};
// Basic instruction class declaration template.
@@ -63,7 +63,7 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/riscv/isa/formats/fp.isa b/src/arch/riscv/isa/formats/fp.isa
index 3de0bb2ff..1f08ca512 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -34,7 +34,7 @@
// Floating point operation instructions
//
def template FloatExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa
index 9b6bc9eb5..5f469dc8d 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -121,18 +121,18 @@ def template LoadStoreDeclare {{
def template EACompDeclare {{
Fault
- eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ eaComp(ExecContext *, Trace::InstRecord *) const;
}};
def template InitiateAccDeclare {{
Fault
- initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ initiateAcc(ExecContext *, Trace::InstRecord *) const;
}};
def template CompleteAccDeclare {{
Fault
- completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+ completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
}};
def template LoadStoreConstructor {{
@@ -146,8 +146,7 @@ def template LoadStoreConstructor {{
def template EACompExecute {{
Fault
- %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -201,8 +200,8 @@ def LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
def template LoadExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -226,7 +225,7 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
Fault
- %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -246,7 +245,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault
- %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -270,7 +269,7 @@ def template LoadCompleteAcc {{
def template StoreExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -303,7 +302,7 @@ def template StoreExecute {{
def template StoreInitiateAcc {{
Fault
- %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -332,7 +331,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault
- %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
return NoFault;
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 4ef241b2c..70d6ada33 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -201,8 +201,8 @@ def template ImmConstructor {{
def template ImmExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -254,7 +254,7 @@ def template BranchDeclare {{
def template BranchExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -313,8 +313,8 @@ def template JumpDeclare {{
def template JumpExecute {{
Fault
- %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ %(class_name)s::execute(
+ ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -446,4 +446,4 @@ def format CSROp(code, *opt_flags) {{
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
-}}; \ No newline at end of file
+}};
diff --git a/src/arch/riscv/isa/formats/unknown.isa b/src/arch/riscv/isa/formats/unknown.isa
index 7a3023a14..aaab21137 100644
--- a/src/arch/riscv/isa/formats/unknown.isa
+++ b/src/arch/riscv/isa/formats/unknown.isa
@@ -68,7 +68,7 @@ output decoder {{
output exec {{
Fault
- Unknown::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+ Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
{
Fault fault = std::make_shared<UnknownInstFault>();
return fault;
diff --git a/src/arch/riscv/isa/micro.isa b/src/arch/riscv/isa/micro.isa
index bd9102d61..61be076b0 100644
--- a/src/arch/riscv/isa/micro.isa
+++ b/src/arch/riscv/isa/micro.isa
@@ -30,8 +30,7 @@
// Authors: Alec Roelke
def template MacroInitiateAcc {{
- Fault initiateAcc(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
+ Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
{
panic("Tried to execute a macroop directly!\n");
return NoFault;
@@ -39,7 +38,7 @@ def template MacroInitiateAcc {{
}};
def template MacroCompleteAcc {{
- Fault completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc,
+ Fault completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
panic("Tried to execute a macroop directly!\n");
@@ -48,7 +47,7 @@ def template MacroCompleteAcc {{
}};
def template MacroExecute {{
- Fault execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const
{
panic("Tried to execute a macroop directly!\n");
return NoFault;