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authorAlec Roelke <ar4jc@virginia.edu>2016-11-30 17:10:28 -0500
committerAlec Roelke <ar4jc@virginia.edu>2016-11-30 17:10:28 -0500
commitee0c261e10c17cb1ce0a1511bb1040318e6d17f9 (patch)
treeb75cbf788a8c4f88dbd09ebb600253c39614b021 /src/arch/riscv/isa
parent84020a8aedd66740c105a06f55412942e9daac30 (diff)
downloadgem5-ee0c261e10c17cb1ce0a1511bb1040318e6d17f9.tar.xz
riscv: [Patch 7/5] Corrected LRSC semantics
RISC-V makes use of load-reserved and store-conditional instructions to enable creation of lock-free concurrent data manipulation as well as ACQUIRE and RELEASE semantics for memory ordering of LR, SC, and AMO instructions (the latter of which do not follow LR/SC semantics). This patch is a correction to patch 4, which added these instructions to the implementation of RISC-V. It modifies locked_mem.hh and the implementations of lr.w, sc.w, lr.d, and sc.d to apply the proper gem5 flags and return the proper values. An important difference between gem5's LLSC semantics and RISC-V's LR/SC ones, beyond the name, is that gem5 uses 0 to indicate failure and 1 to indicate success, while RISC-V is the opposite. Strictly speaking, RISC-V uses 0 to indicate success and nonzero to indicate failure where the value would indicate the error, but currently only 1 is reserved as a failure code by the ISA reference. This is the seventh patch in the series which originally consisted of five patches that added the RISC-V ISA to gem5. The original five patches added all of the instructions and added support for more detailed CPU models and the sixth patch corrected the implementations of Linux constants and structs. There will be an eighth patch that adds some regression tests for the instructions. [Removed some commented-out code from locked_mem.hh.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/isa')
-rw-r--r--src/arch/riscv/isa/decoder.isa4
-rw-r--r--src/arch/riscv/isa/formats/mem.isa7
2 files changed, 8 insertions, 3 deletions
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index d98f94629..eac0652c0 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -218,12 +218,12 @@ decode OPCODE default Unknown::unknown() {
0x3: decode AMOFUNCT {
0x2: LoadReserved::lr_d({{
Rd_sd = Mem_sd;
- }}, aq=AQ, rl=RL);
+ }}, mem_flags=LLSC, aq=AQ, rl=RL);
0x3: StoreCond::sc_d({{
Mem = Rs2;
}}, {{
Rd = result;
- }}, aq=AQ, rl=RL);
+ }}, mem_flags=LLSC, inst_flags=IsStoreConditional, aq=AQ, rl=RL);
format AtomicMemOp {
0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{
Mem_sd = Rs2_sd + Rt_sd;
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa
index bea649c04..69a72dfa8 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -363,6 +363,9 @@ def template StoreCondExecute {{
if (fault == NoFault) {
fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
&result);
+ // RISC-V has the opposite convention gem5 has for success flags,
+ // so we invert the result here.
+ result = !result;
}
if (fault == NoFault) {
@@ -385,7 +388,9 @@ def template StoreCondCompleteAcc {{
%(op_dest_decl)s;
- uint64_t result = pkt->req->getExtraData();
+ // RISC-V has the opposite convention gem5 has for success flags,
+ // so we invert the result here.
+ uint64_t result = !pkt->req->getExtraData();
if (fault == NoFault) {
%(postacc_code)s;