arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation.
The multiply, floating point, and atomic memory instructions will be added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 5
will add support for timing, minor, and detailed CPU models that is missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>

11 files changed, 1593 insertions, 0 deletions

diff --git a/src/arch/riscv/isa/base.isa b/src/arch/riscv/isa/base.isa
new file mode 100644
index 000000000..18233e37a
--- /dev/null
+++ b/src/arch/riscv/isa/base.isa
@@ -0,0 +1,79 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+//          Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Base class for Riscv instructions, and some support functions
+//
+
+//Outputs to decoder.hh
+output header {{
+    using namespace RiscvISA;
+
+    /**
+     * Base class for all RISC-V static instructions.
+     */
+    class RiscvStaticInst : public StaticInst
+    {
+      protected:
+        // Constructor
+        RiscvStaticInst(const char *mnem, MachInst _machInst,
+            OpClass __opClass) : StaticInst(mnem, _machInst, __opClass)
+        {}
+
+        std::string
+        regName(RegIndex reg) const;
+
+        virtual std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+
+      public:
+        void
+        advancePC(RiscvISA::PCState &pc) const
+        {
+            pc.advance();
+        }
+    };
+}};
+
+//Ouputs to decoder.cc
+output decoder {{
+    std::string
+    RiscvStaticInst::regName(RegIndex reg) const
+    {
+        if (reg < FP_Reg_Base) {
+            return std::string(RegisterNames[reg]);
+        } else {
+            return std::string("f") + std::to_string(reg - FP_Reg_Base);
+        }
+    }
+}};
diff --git a/src/arch/riscv/isa/bitfields.isa b/src/arch/riscv/isa/bitfields.isa
new file mode 100644
index 000000000..9a2184453
--- /dev/null
+++ b/src/arch/riscv/isa/bitfields.isa
@@ -0,0 +1,77 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+//          Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Bitfield definitions.
+//
+
+def bitfield OPCODE <6:0>;
+def bitfield NONOPCODE <31:7>;
+
+// R-Type
+def bitfield ALL	<31:0>;
+def bitfield RD     <11:7>;
+def bitfield FUNCT3 <14:12>;
+def bitfield RS1    <19:15>;
+def bitfield RS2    <24:20>;
+def bitfield FUNCT7 <31:25>;
+
+// Bit shifts
+def bitfield SRTYPE <30>;
+def bitfield SHAMT5 <24:20>;
+def bitfield SHAMT6 <25:20>;
+
+// I-Type
+def bitfield IMM12  <31:20>;
+
+// S-Type
+def bitfield IMM5   <11:7>;
+def bitfield IMM7   <31:25>;
+
+// U-Type
+def bitfield IMM20  <31:12>;
+
+// SB-Type
+def bitfield BIMM12BIT11 <7>;
+def bitfield BIMM12BITS4TO1<11:8>;
+def bitfield IMMSIGN <31>;
+def bitfield BIMM12BITS10TO5 <30:25>;
+
+// UJ-Type
+def bitfield UJIMMBITS10TO1 <30:21>;
+def bitfield  UJIMMBIT11 <20>;
+def bitfield UJIMMBITS19TO12 <19:12>;
+
+// System
+def bitfield FUNCT12 <31:20>;
+def bitfield ZIMM <19:15>;
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
new file mode 100644
index 000000000..2f7d91ca8
--- /dev/null
+++ b/src/arch/riscv/isa/decoder.isa
@@ -0,0 +1,332 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// The RISC-V ISA decoder
+//
+
+decode OPCODE default Unknown::unknown() {
+    0x03: decode FUNCT3 {
+        format Load {
+            0x0: lb({{
+                Rd_sd = Mem_sb;
+            }});
+            0x1: lh({{
+                Rd_sd = Mem_sh;
+            }});
+            0x2: lw({{
+                Rd_sd = Mem_sw;
+            }});
+            0x3: ld({{
+                Rd_sd = Mem_sd;
+            }});
+            0x4: lbu({{
+                Rd = Mem_ub;
+            }});
+            0x5: lhu({{
+                Rd = Mem_uh;
+            }});
+            0x6: lwu({{
+                Rd = Mem_uw;
+            }});
+        }
+    }
+
+    0x0f: decode FUNCT3 {
+        format IOp {
+            0x0: fence({{
+            }}, IsNonSpeculative, IsMemBarrier, No_OpClass);
+            0x1: fence_i({{
+            }}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
+        }
+    }
+
+    0x13: decode FUNCT3 {
+        format IOp {
+            0x0: addi({{
+                Rd_sd = Rs1_sd + imm;
+            }});
+            0x1: slli({{
+                Rd = Rs1 << SHAMT6;
+            }});
+            0x2: slti({{
+                Rd = (Rs1_sd < imm) ? 1 : 0;
+            }});
+            0x3: sltiu({{
+                Rd = (Rs1 < (uint64_t)imm) ? 1 : 0;
+            }});
+            0x4: xori({{
+                Rd = Rs1 ^ (uint64_t)imm;
+            }});
+            0x5: decode SRTYPE {
+                0x0: srli({{
+                    Rd = Rs1 >> SHAMT6;
+                }});
+                0x1: srai({{
+                    Rd_sd = Rs1_sd >> SHAMT6;
+                }});
+            }
+            0x6: ori({{
+                Rd = Rs1 | (uint64_t)imm;
+            }});
+            0x7: andi({{
+                Rd = Rs1 & (uint64_t)imm;
+            }});
+        }
+    }
+
+    0x17: UOp::auipc({{
+        Rd = PC + imm;
+    }});
+
+    0x1b: decode FUNCT3 {
+        format IOp {
+            0x0: addiw({{
+                Rd_sd = (int32_t)Rs1 + (int32_t)imm;
+            }});
+            0x1: slliw({{
+                Rd_sd = Rs1_sw << SHAMT5;
+            }});
+            0x5: decode SRTYPE {
+                0x0: srliw({{
+                    Rd = Rs1_uw >> SHAMT5;
+                }});
+                0x1: sraiw({{
+                    Rd_sd = Rs1_sw >> SHAMT5;
+                }});
+            }
+        }
+    }
+
+    0x23: decode FUNCT3 {
+        format Store {
+            0x0: sb({{
+                Mem_ub = Rs2_ub;
+            }});
+            0x1: sh({{
+                Mem_uh = Rs2_uh;
+            }});
+            0x2: sw({{
+                Mem_uw = Rs2_uw;
+            }});
+            0x3: sd({{
+                Mem_ud = Rs2_ud;
+            }});
+        }
+    }
+
+    0x33: decode FUNCT3 {
+        format ROp {
+            0x0: decode FUNCT7 {
+                0x0: add({{
+                    Rd = Rs1_sd + Rs2_sd;
+                }});
+                0x20: sub({{
+                    Rd = Rs1_sd - Rs2_sd;
+                }});
+            }
+            0x1: decode FUNCT7 {
+                0x0: sll({{
+                    Rd = Rs1 << Rs2<5:0>;
+                }});
+            }
+            0x2: decode FUNCT7 {
+                0x0: slt({{
+                    Rd = (Rs1_sd < Rs2_sd) ? 1 : 0;
+                }});
+            }
+            0x3: decode FUNCT7 {
+                0x0: sltu({{
+                    Rd = (Rs1 < Rs2) ? 1 : 0;
+                }});
+            }
+            0x4: decode FUNCT7 {
+                0x0: xor({{
+                    Rd = Rs1 ^ Rs2;
+                }});
+            }
+            0x5: decode FUNCT7 {
+                0x0: srl({{
+                    Rd = Rs1 >> Rs2<5:0>;
+                }});
+                0x20: sra({{
+                    Rd_sd = Rs1_sd >> Rs2<5:0>;
+                }});
+            }
+            0x6: decode FUNCT7 {
+                0x0: or({{
+                    Rd = Rs1 | Rs2;
+                }});
+            }
+            0x7: decode FUNCT7 {
+                0x0: and({{
+                    Rd = Rs1 & Rs2;
+                }});
+            }
+        }
+    }
+
+    0x37: UOp::lui({{
+        Rd = (uint64_t)imm;
+    }});
+
+    0x3b: decode FUNCT3 {
+        format ROp {
+            0x0: decode FUNCT7 {
+                0x0: addw({{
+                    Rd_sd = Rs1_sw + Rs2_sw;
+                }});
+                0x20: subw({{
+                    Rd_sd = Rs1_sw - Rs2_sw;
+                }});
+            }
+            0x1: sllw({{
+                Rd_sd = Rs1_sw << Rs2<4:0>;
+            }});
+            0x5: decode FUNCT7 {
+                0x0: srlw({{
+                    Rd_uw = Rs1_uw >> Rs2<4:0>;
+                }});
+                0x20: sraw({{
+                    Rd_sd = Rs1_sw >> Rs2<4:0>;
+                }});
+            }
+        }
+    }
+
+    0x63: decode FUNCT3 {
+        format SBOp {
+            0x0: beq({{
+                if (Rs1 == Rs2) {
+                    NPC = PC + imm;
+                } else {
+                    NPC = NPC;
+                }
+            }}, IsDirectControl, IsCondControl);
+            0x1: bne({{
+                if (Rs1 != Rs2) {
+                    NPC = PC + imm;
+                } else {
+                    NPC = NPC;
+                }
+            }}, IsDirectControl, IsCondControl);
+            0x4: blt({{
+                if (Rs1_sd < Rs2_sd) {
+                    NPC = PC + imm;
+                } else {
+                    NPC = NPC;
+                }
+            }}, IsDirectControl, IsCondControl);
+            0x5: bge({{
+                if (Rs1_sd >= Rs2_sd) {
+                    NPC = PC + imm;
+                } else {
+                    NPC = NPC;
+                }
+            }}, IsDirectControl, IsCondControl);
+            0x6: bltu({{
+                if (Rs1 < Rs2) {
+                    NPC = PC + imm;
+                } else {
+                    NPC = NPC;
+                }
+            }}, IsDirectControl, IsCondControl);
+            0x7: bgeu({{
+                if (Rs1 >= Rs2) {
+                    NPC = PC + imm;
+                } else {
+                    NPC = NPC;
+                }
+            }}, IsDirectControl, IsCondControl);
+        }
+    }
+
+    0x67: decode FUNCT3 {
+        0x0: Jump::jalr({{
+            Rd = NPC;
+            NPC = (imm + Rs1) & (~0x1);
+        }}, IsIndirectControl, IsUncondControl, IsCall);
+    }
+
+    0x6f: UJOp::jal({{
+        Rd = NPC;
+        NPC = PC + imm;
+    }}, IsDirectControl, IsUncondControl, IsCall);
+
+    0x73: decode FUNCT3 {
+        format IOp {
+            0x0: decode FUNCT12 {
+                0x0: ecall({{
+                    fault = std::make_shared<SyscallFault>();
+                }}, IsSerializeAfter, IsNonSpeculative, IsSyscall, No_OpClass);
+                0x1: ebreak({{
+                    fault = std::make_shared<BreakpointFault>();
+                }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
+                0x100: eret({{
+                    fault = std::make_shared<UnimplementedFault>("eret");
+                }}, No_OpClass);
+            }
+            0x1: csrrw({{
+                Rd = xc->readMiscReg(FUNCT12);
+                xc->setMiscReg(FUNCT12, Rs1);
+            }}, IsNonSpeculative, No_OpClass);
+            0x2: csrrs({{
+                Rd = xc->readMiscReg(FUNCT12);
+                if (Rs1 != 0) {
+                    xc->setMiscReg(FUNCT12, Rd | Rs1);
+                }
+            }}, IsNonSpeculative, No_OpClass);
+            0x3: csrrc({{
+                Rd = xc->readMiscReg(FUNCT12);
+                if (Rs1 != 0) {
+                    xc->setMiscReg(FUNCT12, Rd & ~Rs1);
+                }
+            }}, IsNonSpeculative, No_OpClass);
+            0x5: csrrwi({{
+                Rd = xc->readMiscReg(FUNCT12);
+                xc->setMiscReg(FUNCT12, ZIMM);
+            }}, IsNonSpeculative, No_OpClass);
+            0x6: csrrsi({{
+                Rd = xc->readMiscReg(FUNCT12);
+                if (ZIMM != 0) {
+                    xc->setMiscReg(FUNCT12, Rd | ZIMM);
+                }
+            }}, IsNonSpeculative, No_OpClass);
+            0x7: csrrci({{
+                Rd = xc->readMiscReg(FUNCT12);
+                if (ZIMM != 0) {
+                    xc->setMiscReg(FUNCT12, Rd & ~ZIMM);
+                }
+            }}, IsNonSpeculative, No_OpClass);
+        }
+    }
+}
diff --git a/src/arch/riscv/isa/formats/basic.isa b/src/arch/riscv/isa/formats/basic.isa
new file mode 100644
index 000000000..2a0b823bf
--- /dev/null
+++ b/src/arch/riscv/isa/formats/basic.isa
@@ -0,0 +1,100 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+//          Alec Roelke
+
+// Declarations for execute() methods.
+def template BasicExecDeclare {{
+    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+// Basic instruction class declaration template.
+def template BasicDeclare {{
+    //
+    // Static instruction class for "%(mnemonic)s".
+    //
+    class %(class_name)s : public %(base_class)s
+    {
+      public:
+        /// Constructor.
+        %(class_name)s(MachInst machInst);
+        %(BasicExecDeclare)s
+        using %(base_class)s::generateDisassembly;
+    };
+}};
+
+// Basic instruction class constructor template.
+def template BasicConstructor {{
+    %(class_name)s::%(class_name)s(MachInst machInst)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+    {
+        %(constructor)s;
+    }
+}};
+
+
+// Basic instruction class execute method template.
+def template BasicExecute {{
+    Fault
+    %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+        Trace::InstRecord *traceData) const
+    {
+        Fault fault = NoFault;
+
+        %(op_decl)s;
+        %(op_rd)s;
+        if (fault == NoFault) {
+            %(code)s;
+            if (fault == NoFault) {
+                %(op_wb)s;
+            }
+        }
+        return fault;
+    }
+}};
+
+// Basic decode template.
+def template BasicDecode {{
+    return new %(class_name)s(machInst);
+}};
+
+// Basic decode template, passing mnemonic in as string arg to constructor.
+def template BasicDecodeWithMnemonic {{
+    return new %(class_name)s("%(mnemonic)s", machInst);
+}};
+
+// The most basic instruction format...
+def format BasicOp(code, *flags) {{
+    iop = InstObjParams(name, Name, 'RiscvStaticInst', code, flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
diff --git a/src/arch/riscv/isa/formats/formats.isa b/src/arch/riscv/isa/formats/formats.isa
new file mode 100644
index 000000000..b015f8baa
--- /dev/null
+++ b/src/arch/riscv/isa/formats/formats.isa
@@ -0,0 +1,42 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+//          Alec Roelke
+
+// Include the basic format
+##include "basic.isa"
+
+//Include the type formats
+##include "type.isa"
+##include "mem.isa"
+
+// Include the unknown
+##include "unknown.isa"
+
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa
new file mode 100644
index 000000000..2a00850a2
--- /dev/null
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -0,0 +1,355 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Memory operation instructions
+//
+output header {{
+    class Load : public RiscvStaticInst
+    {
+      public:
+        /// Displacement for EA calculation (signed).
+        int64_t ldisp;
+
+      protected:
+        /// Memory request flags.  See mem_req_base.hh.
+        Request::Flags memAccessFlags;
+
+        /// Constructor
+        Load(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+            : RiscvStaticInst(mnem, _machInst, __opClass), ldisp(IMM12)
+        {
+            if (IMMSIGN > 0)
+                ldisp |= ~((uint64_t)0xFFF);
+        }
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    class Store : public RiscvStaticInst
+    {
+      public:
+        /// Displacement for EA calculation (signed).
+        int64_t sdisp;
+
+      protected:
+        /// Memory request flags.  See mem_req_base.hh.
+        Request::Flags memAccessFlags;
+
+        /// Constructor
+        Store(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
+            : RiscvStaticInst(mnem, _machInst, __opClass), sdisp(IMM5)
+        {
+            sdisp |= IMM7 << 5;
+            if (IMMSIGN > 0)
+                sdisp |= ~((uint64_t)0xFFF);
+        }
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+}};
+
+
+output decoder {{
+    std::string
+    Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+        ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " << ldisp <<
+            '(' << regName(_srcRegIdx[0]) << ')';
+        return ss.str();
+    }
+
+    std::string
+    Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+        ss << mnemonic << ' ' << regName(_srcRegIdx[1]) << ", " << sdisp <<
+            '(' << regName(_srcRegIdx[0]) << ')';
+        return ss.str();
+    }
+}};
+
+def template LoadStoreDeclare {{
+    /**
+     * Static instruction class for "%(mnemonic)s".
+     */
+    class %(class_name)s : public %(base_class)s
+    {
+      public:
+        /// Constructor.
+        %(class_name)s(ExtMachInst machInst);
+
+        %(BasicExecDeclare)s
+
+        %(EACompDeclare)s
+
+        %(InitiateAccDeclare)s
+
+        %(CompleteAccDeclare)s
+    };
+}};
+
+def template EACompDeclare {{
+    Fault
+    eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+def template InitiateAccDeclare {{
+    Fault
+    initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+
+def template CompleteAccDeclare {{
+    Fault
+    completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+def template LoadStoreConstructor {{
+    %(class_name)s::%(class_name)s(ExtMachInst machInst):
+        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+    {
+        %(constructor)s;
+    }
+}};
+
+def template EACompExecute {{
+    Fault
+    %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
+        Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(op_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+            xc->setEA(EA);
+        }
+
+        return fault;
+    }
+}};
+
+let {{
+def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+        base_class, postacc_code='', decode_template=BasicDecode,
+        exec_template_base=''):
+    # Make sure flags are in lists (convert to lists if not).
+    mem_flags = makeList(mem_flags)
+    inst_flags = makeList(inst_flags) # + ['IsNonSpeculative']
+
+    iop = InstObjParams(name, Name, base_class,
+        { 'ea_code':ea_code, 'memacc_code':memacc_code,
+        'postacc_code':postacc_code }, inst_flags)
+
+    if mem_flags:
+        mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
+        s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
+        iop.constructor += s
+
+    # select templates
+
+    fullExecTemplate = eval(exec_template_base + 'Execute')
+    initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
+    completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
+
+    # (header_output, decoder_output, decode_block, exec_output)
+    return (LoadStoreDeclare.subst(iop),
+        LoadStoreConstructor.subst(iop),
+        decode_template.subst(iop),
+        fullExecTemplate.subst(iop) +
+        EACompExecute.subst(iop) +
+        initiateAccTemplate.subst(iop) +
+        completeAccTemplate.subst(iop))
+}};
+
+def template LoadExecute {{
+    Fault
+    %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+        Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(op_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
+            %(memacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
+def template LoadInitiateAcc {{
+    Fault
+    %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+        Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(op_src_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
+        }
+
+        return fault;
+    }
+}};
+
+def template LoadCompleteAcc {{
+    Fault
+    %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
+        Trace::InstRecord *traceData) const
+    {
+        Fault fault = NoFault;
+
+        %(op_decl)s;
+        %(op_rd)s;
+
+        getMem(pkt, Mem, traceData);
+
+        if (fault == NoFault) {
+            %(memacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
+def template StoreExecute {{
+    Fault
+    %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+        Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(op_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            %(memacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                nullptr);
+        }
+
+        if (fault == NoFault) {
+            %(postacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
+def template StoreInitiateAcc {{
+    Fault
+    %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+        Trace::InstRecord *traceData) const
+    {
+        Addr EA;
+        Fault fault = NoFault;
+
+        %(op_decl)s;
+        %(op_rd)s;
+        %(ea_code)s;
+
+        if (fault == NoFault) {
+            %(memacc_code)s;
+        }
+
+        if (fault == NoFault) {
+            fault = writeMemTiming(xc, traceData, Mem, EA,
+                memAccessFlags, nullptr);
+        }
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+
+        return fault;
+    }
+}};
+
+def template StoreCompleteAcc {{
+    Fault
+    %(class_name)s::completeAcc(PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
+        Trace::InstRecord *traceData) const
+    {
+        return NoFault;
+    }
+}};
+
+def format Load(memacc_code, ea_code = {{EA = Rs1 + ldisp;}}, mem_flags=[],
+        inst_flags=[]) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+        'Load', exec_template_base='Load')
+}};
+
+def format Store(memacc_code, ea_code={{EA = Rs1 + sdisp;}}, mem_flags=[],
+        inst_flags=[]) {{
+    (header_output, decoder_output, decode_block, exec_output) = \
+        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+        'Store', exec_template_base='Store')
+}};
diff --git a/src/arch/riscv/isa/formats/type.isa b/src/arch/riscv/isa/formats/type.isa
new file mode 100644
index 000000000..75e842fd2
--- /dev/null
+++ b/src/arch/riscv/isa/formats/type.isa
@@ -0,0 +1,319 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Integer instructions
+//
+output header {{
+    #include <iostream>
+    /**
+     * Base class for R-type operations
+     */
+    class ROp : public RiscvStaticInst
+    {
+      protected:
+        /// Constructor
+        ROp(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : RiscvStaticInst(mnem, _machInst, __opClass)
+        {}
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Base class for I-type operations
+     */
+    class IOp : public RiscvStaticInst
+    {
+      protected:
+        int64_t imm;
+
+        /// Constructor
+        IOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : RiscvStaticInst(mnem, _machInst, __opClass),imm(IMM12)
+        {
+            if (IMMSIGN > 0)
+                imm |= ~((uint64_t)0x7FF);
+        }
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Class for jalr instructions
+     */
+    class Jump : public IOp
+    {
+      protected:
+        Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : IOp(mnem, _machInst, __opClass)
+        {}
+
+        RiscvISA::PCState
+        branchTarget(ThreadContext *tc) const;
+
+        using StaticInst::branchTarget;
+        using IOp::generateDisassembly;
+    };
+
+    /**
+     * Base class for S-type operations
+     */
+    class SOp : public RiscvStaticInst
+    {
+      protected:
+        int64_t imm;
+
+        /// Constructor
+        SOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : RiscvStaticInst(mnem, _machInst, __opClass),imm(0)
+        {
+            imm |= IMM5;
+            imm |= IMM7 << 5;
+            if (IMMSIGN > 0)
+                imm |= ~((uint64_t)0x7FF);
+        }
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Base class for SB-type operations
+     */
+    class SBOp : public RiscvStaticInst
+    {
+      protected:
+        int64_t imm;
+
+        /// Constructor
+        SBOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : RiscvStaticInst(mnem, _machInst, __opClass),imm(0)
+        {
+            imm |= BIMM12BIT11 << 11;
+            imm |= BIMM12BITS4TO1 << 1;
+            imm |= BIMM12BITS10TO5 << 5;
+            if (IMMSIGN > 0)
+                imm |= ~((uint64_t)0xFFF);
+        }
+
+        RiscvISA::PCState
+        branchTarget(const RiscvISA::PCState &branchPC) const;
+
+        using StaticInst::branchTarget;
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Base class for U-type operations
+     */
+    class UOp : public RiscvStaticInst
+    {
+      protected:
+        int64_t imm;
+
+        /// Constructor
+        UOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
+        {
+            int32_t temp = IMM20 << 12;
+            imm = temp;
+        }
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+
+    /**
+     * Base class for UJ-type operations
+     */
+    class UJOp : public RiscvStaticInst
+    {
+      protected:
+        int64_t imm;
+
+        /// Constructor
+        UJOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : RiscvStaticInst(mnem, _machInst, __opClass),imm(0)
+        {
+            imm |= UJIMMBITS19TO12 << 12;
+            imm |= UJIMMBIT11 << 11;
+            imm |= UJIMMBITS10TO1 << 1;
+            if (IMMSIGN > 0)
+                imm |= ~((uint64_t)0xFFFFF);
+        }
+
+        RiscvISA::PCState
+        branchTarget(const RiscvISA::PCState &branchPC) const;
+
+        using StaticInst::branchTarget;
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+}};
+
+//Outputs to decoder.cc
+output decoder {{
+    std::string
+    ROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+        ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " <<
+            regName(_srcRegIdx[0]) << ", " << regName(_srcRegIdx[1]);
+        return ss.str();
+    }
+
+    std::string
+    IOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+        ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " <<
+            regName(_srcRegIdx[0]) << ", " << imm;
+        return ss.str();
+    }
+
+    RiscvISA::PCState
+    Jump::branchTarget(ThreadContext *tc) const
+    {
+        PCState pc = tc->pcState();
+        IntReg Rs1 = tc->readIntReg(_srcRegIdx[0]);
+        pc.set((Rs1 + imm)&~0x1);
+        return pc;
+    }
+
+    std::string
+    SOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+        ss << mnemonic << ' ' << regName(_srcRegIdx[1]) << ", " << imm <<
+            '(' << regName(_srcRegIdx[0]) << ')';
+        return ss.str();
+    }
+
+    RiscvISA::PCState
+    SBOp::branchTarget(const RiscvISA::PCState &branchPC) const
+    {
+        return branchPC.pc() + imm;
+    }
+
+    std::string
+    SBOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+        ss << mnemonic << ' ' << regName(_srcRegIdx[0]) << ", " <<
+            regName(_srcRegIdx[1]) << ", " << imm;
+        return ss.str();
+    }
+
+    std::string
+    UOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+        ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " << imm;
+        return ss.str();
+    }
+
+    RiscvISA::PCState
+    UJOp::branchTarget(const RiscvISA::PCState &branchPC) const
+    {
+        return branchPC.pc() + imm;
+    }
+
+    std::string
+    UJOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+        ss << mnemonic << ' ' << regName(_destRegIdx[0]) << ", " << imm;
+        return ss.str();
+    }
+}};
+
+def format ROp(code, *opt_flags) {{
+    iop = InstObjParams(name, Name, 'ROp', code, opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format IOp(code, *opt_flags) {{
+    iop = InstObjParams(name, Name, 'IOp', code, opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format Jump(code, *opt_flags) {{
+    iop = InstObjParams(name, Name, 'Jump', code, opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format SOp(code, *opt_flags) {{
+    iop = InstObjParams(name, Name, 'SOp', code, opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format SBOp(code, *opt_flags) {{
+    iop = InstObjParams(name, Name, 'SBOp', code, opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format UOp(code, *opt_flags) {{
+    iop = InstObjParams(name, Name, 'UOp', code, opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
+
+def format UJOp(code, *opt_flags) {{
+    iop = InstObjParams(name, Name, 'UJOp', code, opt_flags)
+    header_output = BasicDeclare.subst(iop)
+    decoder_output = BasicConstructor.subst(iop)
+    decode_block = BasicDecode.subst(iop)
+    exec_output = BasicExecute.subst(iop)
+}};
diff --git a/src/arch/riscv/isa/formats/unknown.isa b/src/arch/riscv/isa/formats/unknown.isa
new file mode 100644
index 000000000..7a3023a14
--- /dev/null
+++ b/src/arch/riscv/isa/formats/unknown.isa
@@ -0,0 +1,80 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+//          Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Unknown instructions
+//
+
+output header {{
+    /**
+     * Static instruction class for unknown (illegal) instructions.
+     * These cause simulator termination if they are executed in a
+     * non-speculative mode.  This is a leaf class.
+     */
+    class Unknown : public RiscvStaticInst
+    {
+      public:
+        /// Constructor
+        Unknown(MachInst _machInst)
+            : RiscvStaticInst("unknown", _machInst, No_OpClass)
+        {
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+}};
+
+output decoder {{
+    std::string
+    Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        return csprintf("unknown opcode 0x%02x", OPCODE);
+    }
+}};
+
+output exec {{
+    Fault
+    Unknown::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
+    {
+        Fault fault = std::make_shared<UnknownInstFault>();
+        return fault;
+    }
+}};
+
+def format Unknown() {{
+    decode_block = 'return new Unknown(machInst);\n'
+}};
diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa
new file mode 100644
index 000000000..197133d25
--- /dev/null
+++ b/src/arch/riscv/isa/includes.isa
@@ -0,0 +1,90 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+//          Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// Output include file directives.
+//
+
+output header {{
+#include <iomanip>
+#include <sstream>
+#include <string>
+#include <tuple>
+#include <vector>
+
+#include "cpu/static_inst.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+
+}};
+
+output decoder {{
+#include <cfenv>
+#include <cmath>
+#include <limits>
+#include <string>
+
+#include "arch/riscv/decoder.hh"
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/tlb.hh"
+#include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
+#include "cpu/thread_context.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh"
+#include "sim/full_system.hh"
+
+using namespace RiscvISA;
+}};
+
+output exec {{
+#include <cmath>
+#include <string>
+
+#include "arch/generic/memhelpers.hh"
+#include "arch/riscv/faults.hh"
+#include "arch/riscv/registers.hh"
+#include "base/condcodes.hh"
+#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "mem/request.hh"
+#include "sim/eventq.hh"
+#include "sim/full_system.hh"
+#include "sim/sim_events.hh"
+#include "sim/sim_exit.hh"
+#include "sim/system.hh"
+
+using namespace RiscvISA;
+}};
diff --git a/src/arch/riscv/isa/main.isa b/src/arch/riscv/isa/main.isa
new file mode 100644
index 000000000..2bbfa574d
--- /dev/null
+++ b/src/arch/riscv/isa/main.isa
@@ -0,0 +1,63 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+//          Alec Roelke
+
+////////////////////////////////////////////////////////////////////
+//
+// RISCV ISA description file.
+//
+////////////////////////////////////////////////////////////////////
+
+//Include the C++ include directives
+##include "includes.isa"
+
+////////////////////////////////////////////////////////////////////
+//
+// Namespace statement.  Everything below this line will be in the
+// RiscvISAInst namespace.
+//
+
+namespace RiscvISA;
+
+//Include the bitfield definitions
+##include "bitfields.isa"
+
+//Include the operand_types and operand definitions
+##include "operands.isa"
+
+//Include the base class for riscv instructions, and some support code
+##include "base.isa"
+
+//Include the definitions for the instruction formats
+##include "formats/formats.isa"
+
+//Include the decoder definition
+##include "decoder.isa"
diff --git a/src/arch/riscv/isa/operands.isa b/src/arch/riscv/isa/operands.isa
new file mode 100644
index 000000000..d6bdda399
--- /dev/null
+++ b/src/arch/riscv/isa/operands.isa
@@ -0,0 +1,56 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2015 RISC-V Foundation
+// Copyright (c) 2016 The University of Virginia
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Maxwell Walter
+//          Alec Roelke
+
+def operand_types {{
+    'sb' : 'int8_t',
+    'ub' : 'uint8_t',
+    'sh' : 'int16_t',
+    'uh' : 'uint16_t',
+    'sw' : 'int32_t',
+    'uw' : 'uint32_t',
+    'sd' : 'int64_t',
+    'ud' : 'uint64_t',
+}};
+
+def operands {{
+#General Purpose Integer Reg Operands
+    'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
+    'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
+    'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
+
+#Memory Operand
+    'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),
+
+#Program Counter Operands
+    'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
+    'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
+}};