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authorAlec Roelke <ar4jc@virginia.edu>2017-11-07 14:15:41 -0500
committerAlec Roelke <ar4jc@virginia.edu>2017-11-29 00:55:46 +0000
commiteb02066b31c85d22c67d1ead61048c196653ba1f (patch)
tree1ab43820091dcf702bf2e7ed083eb27bd3cfb313 /src/arch/riscv/isa
parentd3ecb5d406a3dc12c53a20c271db3027b8477c39 (diff)
downloadgem5-eb02066b31c85d22c67d1ead61048c196653ba1f.tar.xz
arch-riscv: Move standard ops out of ISA
This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
Diffstat (limited to 'src/arch/riscv/isa')
-rw-r--r--src/arch/riscv/isa/formats/compressed.isa4
-rw-r--r--src/arch/riscv/isa/formats/standard.isa151
-rw-r--r--src/arch/riscv/isa/includes.isa1
3 files changed, 8 insertions, 148 deletions
diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa
index 1fd2319fd..683795d89 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -67,7 +67,7 @@ def format CROp(code, *opt_flags) {{
def format CIOp(imm_code, code, *opt_flags) {{
regs = ['_destRegIdx[0]','_srcRegIdx[0]']
- iop = InstObjParams(name, Name, 'ImmOp',
+ iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
@@ -78,7 +78,7 @@ def format CIOp(imm_code, code, *opt_flags) {{
def format CUIOp(imm_code, code, *opt_flags) {{
regs = ['_destRegIdx[0]','_srcRegIdx[0]']
- iop = InstObjParams(name, Name, 'UImmOp',
+ iop = InstObjParams(name, Name, 'ImmOp<uint64_t>',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 35c3fa878..e68cedfe2 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -33,147 +33,6 @@
//
// Integer instructions
//
-output header {{
- /**
- * Base class for operations that work only on registers
- */
- class RegOp : public RiscvStaticInst
- {
- protected:
- /// Constructor
- RegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass)
- {}
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-
- /**
- * Base class for operations with signed immediates
- */
- class ImmOp : public RiscvStaticInst
- {
- protected:
- int64_t imm;
-
- /// Constructor
- ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
- {}
-
- virtual std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
- };
-
- /**
- * Base class for operations with unsigned immediates
- */
- class UImmOp : public RiscvStaticInst
- {
- protected:
- uint64_t imm;
-
- /// Constructor
- UImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
- {}
-
- virtual std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
- };
-
- /**
- * Base class for operations with branching
- */
- class BranchOp : public ImmOp
- {
- protected:
- /// Constructor
- BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : ImmOp(mnem, _machInst, __opClass)
- {}
-
- using StaticInst::branchTarget;
-
- virtual RiscvISA::PCState
- branchTarget(ThreadContext *tc) const
- {
- return StaticInst::branchTarget(tc);
- }
-
- virtual RiscvISA::PCState
- branchTarget(const RiscvISA::PCState &branchPC) const
- {
- return StaticInst::branchTarget(branchPC);
- }
-
- virtual std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
- };
-
- /**
- * Base class for system operations
- */
- class SystemOp : public RiscvStaticInst
- {
- public:
- /// Constructor
- SystemOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass)
- {}
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return mnemonic;
- }
- };
-
- /**
- * Base class for CSR operations
- */
- class CSROp : public RiscvStaticInst
- {
- protected:
- uint64_t csr;
- uint64_t uimm;
-
- public:
- /// Constructor
- CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass),
- csr(FUNCT12), uimm(CSRIMM)
- {}
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-}};
-
-//Outputs to decoder.cc
-output decoder {{
- std::string
- RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
- registerName(_srcRegIdx[0]) << ", " <<
- registerName(_srcRegIdx[1]);
- return ss.str();
- }
-
- std::string
- CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
- if (_numSrcRegs > 0)
- ss << registerName(_srcRegIdx[0]) << ", ";
- ss << MiscRegNames.at(csr);
- return ss.str();
- }
-}};
def template ImmDeclare {{
//
@@ -362,7 +221,7 @@ def format ROp(code, *opt_flags) {{
def format IOp(code, *opt_flags) {{
imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
regs = ['_destRegIdx[0]','_srcRegIdx[0]']
- iop = InstObjParams(name, Name, 'ImmOp',
+ iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
@@ -380,7 +239,7 @@ def format BOp(code, *opt_flags) {{
imm |= ~((uint64_t)0xFFF);
"""
regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
- iop = InstObjParams(name, Name, 'BranchOp',
+ iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = BranchDeclare.subst(iop)
@@ -392,7 +251,7 @@ def format BOp(code, *opt_flags) {{
def format Jump(code, *opt_flags) {{
imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
regs = ['_destRegIdx[0]','_srcRegIdx[0]']
- iop = InstObjParams(name, Name, 'BranchOp',
+ iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = JumpDeclare.subst(iop)
@@ -404,7 +263,7 @@ def format Jump(code, *opt_flags) {{
def format UOp(code, *opt_flags) {{
imm_code = 'imm = (int32_t)(IMM20 << 12);'
regs = ['_destRegIdx[0]']
- iop = InstObjParams(name, Name, 'ImmOp',
+ iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
@@ -423,7 +282,7 @@ def format JOp(code, *opt_flags) {{
"""
pc = 'pc.set(pc.pc() + imm);'
regs = ['_destRegIdx[0]']
- iop = InstObjParams(name, Name, 'BranchOp',
+ iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
{'code': code, 'imm_code': imm_code,
'regs': ','.join(regs)}, opt_flags)
header_output = BranchDeclare.subst(iop)
diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa
index 48f2b1957..dfd0f37b4 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,6 +42,7 @@ output header {{
#include <tuple>
#include <vector>
+#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"