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authorAlec Roelke <ar4jc@virginia.edu>2017-03-21 12:51:54 -0400
committerAlec Roelke <ar4jc@virginia.edu>2017-04-05 20:21:04 +0000
commit9d0c9ab12361e009796bdb0b5d074c98d3f75b0e (patch)
tree9bd47ef4af8035a833a676f6f76487b371b84b95 /src/arch/riscv/isa_traits.hh
parentf7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (diff)
downloadgem5-9d0c9ab12361e009796bdb0b5d074c98d3f75b0e.tar.xz
riscv: enable unaligned memory accesses
Sometimes an ld instruction will be split across a cache boundary. Previously RISC-V was set to not allow this. This patch fixes that. Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f Reviewed-on: https://gem5-review.googlesource.com/2341 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/isa_traits.hh')
-rw-r--r--src/arch/riscv/isa_traits.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index f7a2c8762..327d64498 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -65,8 +65,8 @@ const Addr PageBytes = ULL(1) << PageShift;
const ExtMachInst NoopMachInst = 0x00000013;
-// Memory accesses can not be unaligned
-const bool HasUnalignedMemAcc = false;
+// Memory accesses can be unaligned (at least for double-word memory accesses)
+const bool HasUnalignedMemAcc = true;
const bool CurThreadInfoImplemented = false;
const int CurThreadInfoReg = -1;