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| author | Xiaoyu Ma <xiaoyuma@google.com> | 2017-11-30 07:48:52 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-01-12 00:57:56 +0000 |
| commit | 5320a97ced43d4452014ff54c0ba45246db90a00 (patch) | |
| tree | 8048a3c9f79b83deb64b7c5454bd560b2b115208 /src/arch/riscv/process.cc | |
| parent | cc51037e8074949bc9e7638babfb597490d007ec (diff) | |
| download | gem5-5320a97ced43d4452014ff54c0ba45246db90a00.tar.xz | |
sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().
Before this CL, the addTwoLevelCacheHierarchy() function uses the
default L2XBar class as the interconnect between CPU L1 caches and
L2. This CL allows passing a user-defined bus to overwrite the
default L2XBar by adding an optional argument to the function.
Change-Id: I917657272fd4924ee0bed882a226851afba26847
Reviewed-on: https://gem5-review.googlesource.com/7364
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/process.cc')
0 files changed, 0 insertions, 0 deletions