riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A

Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A
extension, which includes atomic memory instructions. These instructions
atomically read a value from memory, modify it with a value contained in a
source register, and store the original memory value in the destination
register and modified value back into memory. Because this requires two
memory accesses and GEM5 does not support two timing memory accesses in
a single instruction, each of these instructions is split into two micro-
ops: A "load" micro-op, which reads the memory, and a "store" micro-op,
which modifies and writes it back.  Each atomic memory instruction also has
two bits that acquire and release a lock on its memory location.
Additionally, there are atomic load and store instructions that only either
load or store, but not both, and can acquire or release memory locks.

Note that because the current implementation of RISC-V only supports one
core and one thread, it doesn't make sense to make use of AMO instructions.
However, they do form a standard extension of the RISC-V ISA, so they are
included mostly as a placeholder for when multithreaded execution is
implemented.  As a result, any tests for their correctness in a future
patch may be abbreviated.

Patch 1 introduced RISC-V and implemented the base instruction set, RV64I;
patch 2 implemented the integer multiply extension, RV64M; and patch 3
implemented the single- and double-precision floating point extensions,
RV64FD.

Patch 5 will add support for timing, minor, and detailed CPU models that
isn't present in patches 1-4.

[Added missing file amo.isa]
[Replaced information removed from initial patch that was missed during
division into multiple patches.]
[Fixed some minor formatting issues.]
[Fixed oversight where LR and SC didn't have both AQ and RL flags.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index cf23c18df..d8977030d 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -68,7 +68,8 @@ typedef uint8_t CCReg; // Not applicable to Riscv
 typedef uint64_t MiscReg;
 
 const int NumIntArchRegs = 32;
-const int NumIntRegs = NumIntArchRegs;
+const int NumMicroIntRegs = 1;
+const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
 const int NumFloatRegs = 32;
 const int NumCCRegs = 0;
 const int NumMiscRegs = 4096;
@@ -79,7 +80,6 @@ const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
 const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs;
 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
 
-
 // Semantically meaningful register indices
 const int ZeroReg = 0;
 const int ReturnAddrReg = 1;
@@ -90,6 +90,7 @@ const int FramePointerReg = 8;
 const int ReturnValueRegs[] = {10, 11};
 const int ReturnValueReg = ReturnValueRegs[0];
 const int ArgumentRegs[] = {10, 11, 12, 13, 14, 15, 16, 17};
+const int AMOTempReg = 32;
 
 const char* const RegisterNames[] = {"zero", "ra", "sp", "gp",
     "tp", "t0", "t1", "t2",