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author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/riscv/registers.hh | |
parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/riscv/registers.hh')
-rw-r--r-- | src/arch/riscv/registers.hh | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index aeebd3fba..2666784e5 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -50,6 +50,7 @@ #include <map> #include <string> +#include "arch/generic/types.hh" #include "arch/isa_traits.hh" #include "arch/riscv/generated/max_inst_regs.hh" #include "base/types.hh" @@ -60,7 +61,6 @@ using RiscvISAInst::MaxInstSrcRegs; using RiscvISAInst::MaxInstDestRegs; const int MaxMiscDestRegs = 1; -typedef uint_fast16_t RegIndex; typedef uint64_t IntReg; typedef uint64_t FloatRegBits; typedef double FloatReg; @@ -74,12 +74,6 @@ const int NumFloatRegs = 32; const int NumCCRegs = 0; const int NumMiscRegs = 4096; -// These help enumerate all the registers for dependence tracking. -const int FP_Reg_Base = NumIntRegs; -const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; -const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; -const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; - // Semantically meaningful register indices const int ZeroReg = 0; const int ReturnAddrReg = 1; |