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| author | Alec Roelke <ar4jc@virginia.edu> | 2016-11-30 17:10:28 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2016-11-30 17:10:28 -0500 |
| commit | 070da984936ea3f1bc0d3ae7d581b59b6733e4fe (patch) | |
| tree | b8e6138549afc2886907a78f37f81dee06f959c6 /src/arch/riscv/registers.hh | |
| parent | e76bfc87640dd236f1527e3f8f19507f0275dad9 (diff) | |
| download | gem5-070da984936ea3f1bc0d3ae7d581b59b6733e4fe.tar.xz | |
riscv: [Patch 2/5] Added RISC-V multiply extension RV64M
Second of five patches adding RISC-V to GEM5. This patch adds the
RV64M extension, which includes integer multiply and divide instructions.
Patch 1 introduced RISC-V and implemented the base instruction set, RV64I.
Patch 3 will implement the floating point extensions, RV64FD; patch 4 will
implement the atomic memory instructions, RV64A; and patch 5 will add
support for timing, minor, and detailed CPU models that is missing from
the first four patches.
[Added mulw instruction that was missed when dividing changes among
patches.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/registers.hh')
0 files changed, 0 insertions, 0 deletions