riscv: add remote gdb support

This patch adds support for debugging with remote GDB to RISC-V. Using
GDB compiled with the RISC-V GNU toolchain, it is possible to pause
and continue execution, view debugging information, etc.  As with the
rest of RISC-V, this does not support full-system mode.

Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d
Reviewed-on: https://gem5-review.googlesource.com/2304
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

1 files changed, 42 insertions, 17 deletions

diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index 1e9dc3e93..735faae02 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -1,8 +1,8 @@
 /*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * Copyright (c) 2009 The University of Edinburgh
- * Copyright (c) 2015 Sven Karlsson
+ * Copyright (c) 2017 The University of Virginia
+ * Copyright 2015 LabWare
+ * Copyright 2014 Google, Inc.
+ * Copyright (c) 2007 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,14 +29,16 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Nathan Binkert
- *          Stephen Hines
- *          Timothy M. Jones
- *          Sven Karlsson
+ *          Boris Shingarov
+ *          Alec Roelke
  */
 
 #ifndef __ARCH_RISCV_REMOTE_GDB_HH__
 #define __ARCH_RISCV_REMOTE_GDB_HH__
 
+#include <string>
+
+#include "arch/riscv/registers.hh"
 #include "base/remote_gdb.hh"
 
 class System;
@@ -47,20 +49,43 @@ namespace RiscvISA
 
 class RemoteGDB : public BaseRemoteGDB
 {
-  public:
-    RemoteGDB(System *system, ThreadContext *context);
+  protected:
+    static const int ExplicitCSRs = 4;
+
+    bool acc(Addr addr, size_t len);
 
-    BaseGdbRegCache *
-    gdbRegs();
+    class RiscvGdbRegCache : public BaseGdbRegCache
+    {
+      using BaseGdbRegCache::BaseGdbRegCache;
+      private:
+        struct {
+            IntReg gpr[NumIntArchRegs];
+            IntReg pc;
+            FloatRegBits fpr[NumFloatRegs];
 
-    bool
-    acc(Addr, size_t);
+            MiscReg csr_base;
+            uint32_t fflags;
+            uint32_t frm;
+            uint32_t fcsr;
+            MiscReg csr[NumMiscRegs - ExplicitCSRs];
+        } __attribute__((__packed__)) r;
+      public:
+        char *data() const { return (char *)&r; }
+        size_t size() const { return sizeof(r); }
+        void getRegs(ThreadContext*);
+        void setRegs(ThreadContext*) const;
 
-    void
-    getregs();
+        const std::string
+        name() const
+        {
+            return gdb->name() + ".RiscvGdbRegCache";
+        }
+    };
 
-    void
-    setregs();
+
+  public:
+    RemoteGDB(System *_system, ThreadContext *tc);
+    BaseGdbRegCache *gdbRegs();
 };
 
 } // namespace RiscvISA