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| author | Robert <robert.scheffel1@tu-dresden.de> | 2018-03-13 14:29:00 +0100 |
|---|---|---|
| committer | Robert Scheffel <robert.scheffel1@tu-dresden.de> | 2018-07-09 11:17:11 +0000 |
| commit | 5de8ca95506a5f15bfbfdd2ca9babd282a882d1f (patch) | |
| tree | 1bc429aa1896dea5167e37000428d157b1a0b710 /src/arch/riscv/system.hh | |
| parent | 98cbcbb54f56475759fae747b60e47568617640f (diff) | |
| download | gem5-5de8ca95506a5f15bfbfdd2ca9babd282a882d1f.tar.xz | |
arch-riscv: enable rudimentary fs simulation
These changes enable a simple binary to be simulated in full system mode.
Additionally, a new fault was implemented.
It is executed once the CPU is initialized.
This fault clears all interrupts and sets the pc to a reset vector.
Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88
Reviewed-on: https://gem5-review.googlesource.com/9061
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/system.hh')
| -rw-r--r-- | src/arch/riscv/system.hh | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/riscv/system.hh b/src/arch/riscv/system.hh index aa5eaaa3a..85b8d6a4b 100644 --- a/src/arch/riscv/system.hh +++ b/src/arch/riscv/system.hh @@ -29,6 +29,7 @@ * Authors: Ali Saidi * Nathan Binkert * Jaidev Patwardhan + * Robert Scheffel */ #ifndef __ARCH_RISCV_SYSTEM_HH__ @@ -47,11 +48,23 @@ class RiscvSystem : public System { + protected: + // checker for bare metal application + bool _isBareMetal; + // entry point for simulation + Addr _resetVect; + public: typedef RiscvSystemParams Params; RiscvSystem(Params *p); ~RiscvSystem(); + // return reset vector + Addr resetVect() const { return _resetVect; } + + // return bare metal checker + bool isBareMetal() const { return _isBareMetal; } + virtual bool breakpoint(); public: |