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| author | Alec Roelke <ar4jc@virginia.edu> | 2016-11-30 17:10:28 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2016-11-30 17:10:28 -0500 |
| commit | 1229b3b62303e00693cfb052fca6e4f7879cf0af (patch) | |
| tree | 39cf4ee7cbc80de16ca9c748f6852afdf3a9b3df /src/arch/riscv/tlb.hh | |
| parent | 070da984936ea3f1bc0d3ae7d581b59b6733e4fe (diff) | |
| download | gem5-1229b3b62303e00693cfb052fca6e4f7879cf0af.tar.xz | |
riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD
Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD
extensions, which include single- and double-precision floating point
instructions.
Patch 1 introduced RISC-V and implemented the base instruction set, RV64I
and patch 2 implemented the integer multiply extension, RV64M.
Patch 4 will implement the atomic memory instructions, RV64A, and patch
5 will add support for timing, minor, and detailed CPU models that is
missing from the first four patches.
[Fixed exception handling in floating-point instructions to conform better
to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V
simulator.]
[Fixed style errors in decoder.isa.]
[Fixed some fuzz caused by modifying a previous patch.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/riscv/tlb.hh')
0 files changed, 0 insertions, 0 deletions